chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
210
migration/project-root/ppc-manual/vmx/vsel.md
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migration/project-root/ppc-manual/vmx/vsel.md
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# `vsel` — Vector Conditional Select
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VA](../forms/VA.md) · **Opcode:** `0x1000002a`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vsel` | `vsel` | — | Vector Conditional Select |
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| `vsel128` | `vsel128` | — | Vector128 Conditional Select |
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## Syntax
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```asm
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vsel [VD], [VA], [VB], [VC]
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vsel128 [VD], [VA], [VB], [VD]
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```
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## Encoding
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### `vsel` — form `VA`
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- **Opcode word:** `0x1000002a`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `42`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT` | destination vector register |
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| 11–15 | `VRA` | source A |
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| 16–20 | `VRB` | source B |
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| 21–25 | `VRC` | source C / shift |
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| 26–31 | `XO` | extended opcode (6 bits) |
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### `vsel128` — form `VX128`
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- **Opcode word:** `0x14000350`
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- **Primary opcode (bits 0–5):** `5`
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- **Extended opcode:** `848`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4 or 5) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `VA128l` | source A low 5 bits |
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| 16–20 | `VB128l` | source B low 5 bits |
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| 21 | `VA128H` | source A high bit |
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| 22 | `—` | reserved |
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| 23–25 | `VC` | optional VC / XO sub-field |
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| 26 | `VA128h` | source A middle bit |
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| 27 | `—` | reserved |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `VB128h` | source B high 2 bits |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vsel: read; vsel128: read | Source A vector register. |
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| `VB` | vsel: read; vsel128: read | Source B vector register. |
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| `VC` | vsel: read | Source C vector register / 3-bit selector. |
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| `VD` | vsel: write; vsel128: read; vsel128: write | Destination vector register. |
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## Register Effects
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### `vsel`
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- **Reads (always):** `VA`, `VB`, `VC`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `vsel128`
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- **Reads (always):** `VA`, `VB`, `VD`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vsel`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsel"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1386`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1386)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:121`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L121)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:585`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L585)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2253-2275`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2253-L2275)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vsel | PpcOpcode::vsel128 => {
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// vD = (vA & ~vC) | (vB & vC)
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let (va, vb, vd);
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let vc;
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if matches!(instr.opcode, PpcOpcode::vsel128) {
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va = instr.va128();
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vb = instr.vb128();
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vd = instr.vd128();
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vc = vd; // for 128, vC is encoded in vD field
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} else {
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va = instr.ra();
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vb = instr.rb();
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vd = instr.rd();
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vc = instr.rc();
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}
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let a = ctx.vr[va].as_u32x4();
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let b = ctx.vr[vb].as_u32x4();
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let c = ctx.vr[vc].as_u32x4();
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let mut r = [0u32; 4];
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for i in 0..4 { r[i] = (a[i] & !c[i]) | (b[i] & c[i]); }
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ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
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ctx.pc += 4;
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}
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```
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</details>
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**`vsel128`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsel128"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1389`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1389)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:121`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L121)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:629`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L629)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2253-2275`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2253-L2275)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vsel | PpcOpcode::vsel128 => {
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// vD = (vA & ~vC) | (vB & vC)
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let (va, vb, vd);
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let vc;
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if matches!(instr.opcode, PpcOpcode::vsel128) {
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va = instr.va128();
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vb = instr.vb128();
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vd = instr.vd128();
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vc = vd; // for 128, vC is encoded in vD field
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} else {
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va = instr.ra();
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vb = instr.rb();
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vd = instr.rd();
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vc = instr.rc();
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}
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let a = ctx.vr[va].as_u32x4();
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let b = ctx.vr[vb].as_u32x4();
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let c = ctx.vr[vc].as_u32x4();
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let mut r = [0u32; 4];
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for i in 0..4 { r[i] = (a[i] & !c[i]) | (b[i] & c[i]); }
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ctx.vr[vd] = xenia_types::Vec128::from_u32x4_array(r);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Per-bit select.** `VD = (VA & ~VC) | (VB & VC)`. Evaluated bit-by-bit across the full 128-bit register — not per-lane. Any granularity (byte / half / word) is valid because each bit is independent.
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- **Classic "bitwise conditional move".** The canonical use is: compare produces an all-ones / all-zeros mask in `VC`, then `vsel` picks between two data vectors. Because the mask is all-or-nothing per lane, `vsel` behaves identically to a per-lane conditional move in that common case.
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- **Mask does not need to be all-ones / all-zeros.** Partial masks produce interleaved bits, which is useful for bitfield merges.
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- **`vsel128` read pattern is atypical:** the destination `VD` is **also an input**. The VMX128 encoding reuses the destination's 7 bits to carry one of the three source operands (xenia's interpreter arm handles this — see `vsel128` Register Effects above). Compilers express this as `vsel v3, v4, v5, v3` even though `v3` is also the destination.
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- **No flags, no VSCR.** No dedicated VMX128 separate-control-register sibling; `vsel128` covers the VMX128 case.
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- **Cheaper than `vand` + `vandc` + `vor`.** `vsel` is a single-cycle primitive on Xenon.
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## Related Instructions
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- [`vand`](vand.md), [`vandc`](vandc.md), [`vor`](vor.md), [`vnor`](vnor.md), [`vxor`](vxor.md) — the boolean primitives `vsel` replaces when composed.
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- [`vcmpequb`](vcmpequb.md), [`vcmpequh`](vcmpequh.md), [`vcmpequw`](vcmpequw.md), [`vcmpgtsb`](vcmpgtsb.md) and relatives — the usual source of the select mask.
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- [`vperm`](vperm.md) — byte-level permute; uses an index vector rather than a boolean mask.
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## IBM Reference
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- [AIX 7.3 — `vsel` (Vector Conditional Select)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vsel-vector-conditional-select-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 3 — Logical Operations](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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Block a user