xenia-rs/migration/project-root/ppc-manual/alu/andisx.md

andis. — AND Immediate Shifted

Category: Integer ALU · Form: D · Opcode: 0x74000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
andis.	andis.	—	AND Immediate Shifted

Syntax

andis. [RA], [RS], [UIMM]

Encoding

andis. — form D

• Opcode word: 0x74000000
• Primary opcode (bits 0–5): 29
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
RS	andis.: read	Source GPR (alias for RD in some stores).
UIMM	andis.: read	16-bit unsigned immediate. Zero-extended.
RA	andis.: write	Source GPR (r0–r31).
CR	andis.: write	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

andis.

• Reads (always): RS, UIMM
• Reads (conditional): none
• Writes (always): RA, CR
• Writes (conditional): none

Status-Register Effects

• andis.: CR0 ← signed-compare(result, 0) with SO ← XER[SO] (always).

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

andis.

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="andis."
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:665
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:9
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:352
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:505-511

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::andisx => {
            // PPCBUG-023: 32-bit ABI CR0 view. `andis. rA, rS, 0x8000` to test
            // sign bit of a 32-bit word now correctly classifies bit 31 = 1 as LT.
            ctx.gpr[instr.ra()] = ctx.gpr[instr.rs()] & ((instr.uimm16() as u64) << 16);
            ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Always Rc=1. Like andix, the dot is part of the mnemonic; no plain andis exists.
• Immediate is shifted left 16, zero-extended. Effective mask is (UIMM << 16) & 0xFFFFFFFF, so the only bits that can survive in RA are bits 32–47 (in PowerISA bit numbering, equivalent to bits 16–31 of the low 32 bits) of RS. Bits 0–31 and bits 48–63 of RA are forced to zero.
• Together with andi. covers the entire low 32 bits. Any 32-bit mask can be applied with andis. + andi. (two instructions). Larger masks need rlwinm or a constructed register operand to andx.
• High 32 bits of result are always zero. Because the immediate is at bits 32–47, no information from RS[0:31] survives. Useful as a quick "extract bits 32–47, zero the rest" primitive.
• CR0 update is unconditional and uses the standard signed-compare-to-zero semantics with XER[SO] folded into SO.
• 64-bit CR update on Xenon, 32-bit in xenia-rs. The result as i32 as i64 truncation in interpreter.rs:326 is harmless: the result is bounded by 0x00000000_FFFF0000, which fits the 32-bit window exactly.

Related Instructions

• andix — companion (immediate not shifted).
• andx, andcx — register AND.
• oris, xoris — sister immediate-shifted logicals.
• rlwinmx — full mask-and-rotate when the bits of interest aren't aligned to a 16-bit boundary.

IBM Reference

• AIX 7.3 — andis. (AND Immediate Shifted)