xenia-rs/migration/project-root/ppc-manual/alu/rlwinmx.md

rlwinmx — Rotate Left Word Immediate then AND with Mask

Category: Integer ALU · Form: M · Opcode: 0x54000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rlwinm	rlwinmx	—	Rotate Left Word Immediate then AND with Mask
rlwinm.	rlwinmx	Rc=1	Rotate Left Word Immediate then AND with Mask

Syntax

rlwinm[Rc] [RA], [RS], [SH], [MB], [ME]

Encoding

rlwinmx — form M

• Opcode word: 0x54000000
• Primary opcode (bits 0–5): 21
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	SH/RB	shift amount or source B
21–25	MB	mask begin
26–30	ME	mask end
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rlwinmx: read	Source GPR (alias for RD in some stores).
SH	rlwinmx: read	Shift amount.
MB	rlwinmx: read	Mask begin bit.
ME	rlwinmx: read	Mask end bit.
RA	rlwinmx: write	Source GPR (r0–r31).
CR	rlwinmx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rlwinmx

• Reads (always): RS, SH, MB, ME
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rlwinmx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rlwinmx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="rlwinmx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:1046
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:61
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:345
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:725-736

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::rlwinmx => {
            let rs = ctx.gpr[instr.rs()] as u32;
            let sh = instr.sh();
            let mb = instr.mb();
            let me = instr.me();
            let rotated = rs.rotate_left(sh);
            let mask = rlw_mask(mb, me);
            ctx.gpr[instr.ra()] = (rotated & mask) as u64;
            // PPCBUG-024: 32-bit ABI CR0 view.
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• RA ← ROTL32(RS[32:63], SH) & MASK(MB, ME). Take the low 32 bits of RS, rotate them left by SH, AND with a 32-bit mask. The high 32 bits of RA are zero (as u64 zero-extension on the result).
• The 32-bit Swiss army knife. Most 32-bit shift/extract simplified mnemonics expand to this single instruction:
  • slwi RA, RS, n ≡ rlwinm RA, RS, n, 0, 31-n — logical left shift.
  • srwi RA, RS, n ≡ rlwinm RA, RS, 32-n, n, 31 — logical right shift.
  • clrlwi RA, RS, n ≡ rlwinm RA, RS, 0, n, 31 — clear high n bits.
  • clrrwi RA, RS, n ≡ rlwinm RA, RS, 0, 0, 31-n — clear low n bits.
  • extlwi, extrwi, clrlslwi — full mnemonic family in PowerISA appendix.
• Mask convention MB..ME is contiguous when MB ≤ ME. When MB > ME, the mask is the complement of bits ME+1..MB-1 — a donut/wrap mask. Xenia's rlw_mask handles both.
• SH is 5 bits, rotate amount 0..31.
• Rc=1 CR0 update truncates to 32 bits in xenia-rs. interpreter.rs:518. Since the result fits in 32 bits, the truncation matches spec exactly.
• No XER effect.

Related Instructions

• rlwimix — same mask family with read-modify-write insert.
• rlwnmx — register-shift version.
• rldiclx, rldicrx — 64-bit cousins.
• slwx, srwx, srawix — straight 32-bit shift instructions.
• slwi, srwi, clrlwi, clrrwi, extlwi, extrwi (simplified mnemonics).

IBM Reference

• AIX 7.3 — rlwinm (Rotate Left Word Immediate then AND with Mask)
• AIX 7.3 — Rotate / shift simplified mnemonics