xenia-rs/migration/project-root/ppc-manual/alu/divwux.md

divwux — Divide Word Unsigned

Category: Integer ALU · Form: XO · Opcode: 0x7c000396

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
divwu	divwux	—	Divide Word Unsigned
divwuo	divwux	OE=1	Divide Word Unsigned
divwu.	divwux	Rc=1	Divide Word Unsigned
divwuo.	divwux	OE=1, Rc=1	Divide Word Unsigned

Syntax

divwu[OE][Rc] [RD], [RA], [RB]

Encoding

divwux — form XO

• Opcode word: 0x7c000396
• Primary opcode (bits 0–5): 31
• Extended opcode: 459
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	divwux: read	Source GPR (r0–r31).
RB	divwux: read	Source GPR.
RD	divwux: write	Destination GPR.
OE	divwux: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.
CR	divwux: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

divwux

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): OE, CR

Status-Register Effects

• divwux: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.

Operation (pseudocode)

RT <- ((RA)[32:63] /u (RB)[32:63]) zero-extended to 64 ; undefined if RB=0

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

divwux

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="divwux"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:269
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:21
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:877
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:413-430

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::divwux => {
            // PPCBUG-020: 32-bit ABI CR0 view.
            let ra = ctx.gpr[instr.ra()] as u32;
            let rb = ctx.gpr[instr.rb()] as u32;
            let ov = overflow::divw_ov_unsigned(rb);
            if ov {
                ctx.gpr[instr.rd()] = 0;
            } else {
                ctx.gpr[instr.rd()] = (ra / rb) as u64;
            }
            if instr.oe() {
                overflow::apply(ctx, ov);
            }
            if instr.rc_bit() {
                ctx.update_cr_signed(0, ctx.gpr[instr.rd()] as u32 as i32 as i64);
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• 32-bit operands, zero-extended result. Both RA and RB are read as their low 32 bits, unsigned (as u32); the quotient is computed as u32, then zero-extended to 64 bits. The high 32 bits of RA/RB are ignored on input and the high 32 bits of RT are zero on output.
• Single undefined case. Division by zero (RB == 0); xenia-rs returns 0 (interpreter.rs:251). No INT_MIN/-1 case because the operands are unsigned.
• No trap on Xenon. Same as divdx — silent undefined result.
• OE=1 should set XER[OV] on RB == 0; xenia-rs ignores this.
• Rc=1 CR0 update. interpreter.rs:256 uses as i32 as i64 — for an unsigned 32-bit quotient stored in the low 32 bits with high zeros, this matches spec exactly; the i32 view will be negative iff the unsigned quotient ≥ 2^31. Worth flagging when comparing CR0 against zero after a large divwu.
• Truncating quotient. Floor division for non-negative integers; matches C unsigned semantics.
• Same slow non-pipelined latency as divw.

Related Instructions

• divwx — signed 32-bit divide.
• divdux, divdx — 64-bit variants.
• mullwx — pair to recover the remainder.
• cmplwi (simplified) — guard the divisor.

IBM Reference

• AIX 7.3 — divwu (Divide Word Unsigned)