xenia-rs/migration/project-root/ppc-manual/alu/divdx.md

divdx — Divide Doubleword

Category: Integer ALU · Form: XO · Opcode: 0x7c0003d2

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
divd	divdx	—	Divide Doubleword
divdo	divdx	OE=1	Divide Doubleword
divd.	divdx	Rc=1	Divide Doubleword
divdo.	divdx	OE=1, Rc=1	Divide Doubleword

Syntax

divd[OE][Rc] [RD], [RA], [RB]

Encoding

divdx — form XO

• Opcode word: 0x7c0003d2
• Primary opcode (bits 0–5): 31
• Extended opcode: 489
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	divdx: read	Source GPR (r0–r31).
RB	divdx: read	Source GPR.
RD	divdx: write	Destination GPR.
OE	divdx: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.
CR	divdx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

divdx

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): OE, CR

Status-Register Effects

• divdx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.

Operation (pseudocode)

RT <- (RA) /s (RB)                       ; undefined if RB=0 or (RA=-2^63 and RB=-1)

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

divdx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="divdx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:192
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:21
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:878
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:463-479

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::divdx => {
            let ra = ctx.gpr[instr.ra()] as i64;
            let rb = ctx.gpr[instr.rb()] as i64;
            let ov = overflow::divd_ov_signed(ra, rb);
            if ov {
                ctx.gpr[instr.rd()] = 0;
            } else {
                ctx.gpr[instr.rd()] = (ra / rb) as u64;
            }
            if instr.oe() {
                overflow::apply(ctx, ov);
            }
            if instr.rc_bit() {
                ctx.update_cr_signed(0, ctx.gpr[instr.rd()] as i64);
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Two undefined-behaviour cases. Division by zero (RB == 0) and signed-min divided by negative-one (RA == INT64_MIN && RB == -1, which would mathematically produce 2^63, unrepresentable in i64). PowerISA leaves RT boundedly undefined in both cases; xenia-rs returns 0 (interpreter.rs:293). Matching this behaviour bit-for-bit is a defacto-spec on Xenon.
• No exception raised. Xenon does not trap on either undefined case; the consuming code is expected to have validated RB first, e.g. with cmpdi/bne. If you need a trap, follow the divide with tw/twi (these live outside the ALU page set).
• OE=1 should set XER[OV] for both undefined cases plus any operand triggering overflow; xenia-rs does not implement the OE branch.
• Rc=1 CR0 update is correctly 64-bit here. Unlike most ALU pages, interpreter.rs:298 uses as i64 (no as i32 truncation) — divide is one of the few xenia-rs instructions that already matches Xenon spec for the CR0 width.
• Latency. Integer divide is the slowest ALU instruction on Xenon — 70+ cycles, non-pipelined. Hot inner loops avoid it via reciprocal-multiply or shift; expect to see mulhwu-based reciprocals in optimised disassembly.
• Rounds toward zero. The signed quotient truncates toward zero, matching C99/C++11 / semantics. Use mulldx and a subtract to recover the remainder; there is no divmod instruction.

Related Instructions

• divdux — unsigned 64-bit divide.
• divwx, divwux — 32-bit signed/unsigned variants.
• mulldx, mulhdx — multiply pair used to compute the remainder.
• cmpi, cmp — guard the divisor before invoking divide.

IBM Reference

• AIX 7.3 — divd (Divide Doubleword)
• PowerISA v2.07B, Book I, §3.3.9 — defines the boundedly-undefined behaviour for RB=0 and INT_MIN/−1.