xenia-rs/migration/project-root/ppc-manual/alu/eqvx.md

eqvx — Equivalent

Category: Integer ALU · Form: X · Opcode: 0x7c000238

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
eqv	eqvx	—	Equivalent
eqv.	eqvx	Rc=1	Equivalent

Syntax

eqv[Rc] [RA], [RS], [RB]

Encoding

eqvx — form X

• Opcode word: 0x7c000238
• Primary opcode (bits 0–5): 31
• Extended opcode: 284
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	eqvx: read	Source GPR (alias for RD in some stores).
RB	eqvx: read	Source GPR.
RA	eqvx: write	Source GPR (r0–r31).
CR	eqvx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

eqvx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• eqvx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- ~((RS) ^ (RB))

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

eqvx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="eqvx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:704
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:25
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:796
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:578-586

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::eqvx => {
            // PPCBUG-031: `eqv rA, rA, rA` is a common "set to all-ones" idiom;
            // 64-bit form gave 0xFFFFFFFFFFFFFFFF but 32-bit ABI expects 0x00000000FFFFFFFF.
            let rs32 = ctx.gpr[instr.rs()] as u32;
            let rb32 = ctx.gpr[instr.rb()] as u32;
            ctx.gpr[instr.ra()] = (!(rs32 ^ rb32)) as u64;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• NXOR / equivalence. RA ← ~(RS XOR RB). A bit in RA is 1 iff the corresponding bits of RS and RB are equal. Useful as a per-bit equality test feeding into a cntlzw for run-length analysis.
• Idiom: eqv RA, RS, RS sets every bit to 1 — a one-instruction RA = -1. Cheaper than li RA, -1 followed by oris/ori for full 64-bit -1.
• Operand convention is X-form (RA is destination; RS, RB are sources).
• 64-bit operation on Xenon; ~ is full 64-bit on u64.
• No OE, no XER side effects. Only Rc=1 updates CR0.
• 64-bit CR update on Xenon, 32-bit in xenia-rs. interpreter.rs:382 truncates with as i32 as i64. Significant when the high 32 bits of the result differ from the low 32 — e.g. eqv. RA, RS, RB with RS == 0x1_0000_0000, RB == 0: spec sees 0xFFFFFFFE_FFFFFFFF (LT), xenia sees 0xFFFFFFFFFFFFFFFF (LT) — actually both negative here, but the exact CR contents differ for finer cases.

Related Instructions

• xorx — base XOR (eqv is xor then not).
• andx, orx, nandx, norx, andcx, orcx — full logical family.
• xori, xoris — immediate XOR (no immediate eqv exists).

IBM Reference

• AIX 7.3 — eqv (Equivalent)