xenia-rs/migration/project-root/ppc-manual/alu/nandx.md

nandx — NAND

Category: Integer ALU · Form: X · Opcode: 0x7c0003b8

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
nand	nandx	—	NAND
nand.	nandx	Rc=1	NAND

Syntax

nand[Rc] [RA], [RS], [RB]

Encoding

nandx — form X

• Opcode word: 0x7c0003b8
• Primary opcode (bits 0–5): 31
• Extended opcode: 476
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	nandx: read	Source GPR (alias for RD in some stores).
RB	nandx: read	Source GPR.
RA	nandx: write	Source GPR (r0–r31).
CR	nandx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

nandx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• nandx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- ~((RS) & (RB))

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

nandx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="nandx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:753
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:59
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:812
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:570-577

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::nandx => {
            // PPCBUG-030: same shape — operate in u32.
            let rs32 = ctx.gpr[instr.rs()] as u32;
            let rb32 = ctx.gpr[instr.rb()] as u32;
            ctx.gpr[instr.ra()] = (!(rs32 & rb32)) as u64;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• RA ← ~(RS AND RB). Bit-wise NAND. Since nand RA, RS, RS = ~RS (NOT-OR-self), the simplified mnemonic not RA, RS assembles to nor RA, RS, RS (note: NOR, not NAND). NAND-self is equivalent — both produce ~RS — but the assembler prefers the NOR form by convention.
• Operand convention is X-form (RA destination, RS/RB sources).
• 64-bit operation on Xenon; ~ operates on the full u64.
• No OE or XER side effects. Only Rc=1 updates CR0 (signed compare to zero).
• 64-bit CR update on Xenon, 32-bit in xenia-rs. interpreter.rs:377 truncates with as i32 as i64. NAND results frequently have all-ones high bits when the low half AND is non-saturating, so the truncation can change CR0 semantics in subtle ways — call out as a quirk if reproducing CR-sensitive behaviour.
• Idiom: NAND of two equal values produces NOT. nand. RA, RS, RS ≡ ~RS with CR0 update. Sometimes used by compilers when not. is unavailable in their tablegen.

Related Instructions

• andx, andcx — base AND family.
• norx — assembler-preferred form for "NOT" via nor RA, RS, RS.
• eqvx — NXOR.
• orx, orcx, xorx — full logical family.

IBM Reference

• AIX 7.3 — nand (NAND)