xenia-rs/migration/project-root/ppc-manual/alu/mulldx.md

mulldx — Multiply Low Doubleword

Category: Integer ALU · Form: XO · Opcode: 0x7c0001d2

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mulld	mulldx	—	Multiply Low Doubleword
mulldo	mulldx	OE=1	Multiply Low Doubleword
mulld.	mulldx	Rc=1	Multiply Low Doubleword
mulldo.	mulldx	OE=1, Rc=1	Multiply Low Doubleword

Syntax

mulld[OE][Rc] [RD], [RA], [RB]

Encoding

mulldx — form XO

• Opcode word: 0x7c0001d2
• Primary opcode (bits 0–5): 31
• Extended opcode: 233
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	mulldx: read	Source GPR (r0–r31).
RB	mulldx: read	Source GPR.
RD	mulldx: write	Destination GPR.
CR	mulldx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
OE	mulldx: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.

Register Effects

mulldx

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): CR, OE

Status-Register Effects

• mulldx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.

Operation (pseudocode)

RT <- ((RA) * (RB))[64:127]               ; low 64 of signed 64×64

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mulldx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="mulldx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:368
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:57
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:872
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:433-444

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::mulldx => {
            let ra = ctx.gpr[instr.ra()] as i64;
            let rb = ctx.gpr[instr.rb()] as i64;
            ctx.gpr[instr.rd()] = ra.wrapping_mul(rb) as u64;
            if instr.oe() {
                overflow::apply(ctx, overflow::mulld_ov(ra, rb));
            }
            if instr.rc_bit() {
                ctx.update_cr_signed(0, ctx.gpr[instr.rd()] as i64);
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Returns the low 64 bits of a signed 64×64 product. Equivalent to (int64_t)(RA * RB) modulo 2^64. Both operands are full 64-bit signed; no truncation on input.
• High bits silently lost. The high 64 bits of the true product are discarded; pair with mulhdx (signed) or mulhdux (unsigned) to recover them.
• OE=1 should set XER[OV] when the 128-bit signed product cannot be represented in 64 bits — i.e. when mulhd RA, RB is not the sign-extension of mulld RA, RB. Xenia-rs does not implement OE (interpreter.rs:264 has no oe() branch).
• Rc=1 CR0 update is correctly 64-bit. interpreter.rs:269 uses as i64 — full 64-bit signed compare. One of the few non-truncating CR0 sites in xenia-rs; means mulld. gives spec-correct CR0 even when the result has non-zero high 32 bits.
• Same instruction for signed and unsigned low halves. Modular arithmetic is identical; only the high half (mulhd vs mulhdu) distinguishes the interpretations.
• Multi-cycle latency — slowest of the ALU pipelines after divide.

Related Instructions

• mulhdx, mulhdux — signed/unsigned high halves of the same multiply.
• mullwx — 32-bit signed multiply (low 64).
• mulli — D-form: RT ← (RA[32:63]) × SIMM.
• divdx, divdux — 64-bit divide, often paired with mulld for remainders.

IBM Reference

• AIX 7.3 — mulld (Multiply Low Doubleword)