xenia-rs/migration/project-root/ppc-manual/alu/sldx.md

sldx — Shift Left Doubleword

Category: Integer ALU · Form: X · Opcode: 0x7c000036

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
sld	sldx	—	Shift Left Doubleword
sld.	sldx	Rc=1	Shift Left Doubleword

Syntax

sld[Rc] [RA], [RS], [RB]

Encoding

sldx — form X

• Opcode word: 0x7c000036
• Primary opcode (bits 0–5): 31
• Extended opcode: 27
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	sldx: read	Source GPR (alias for RD in some stores).
RB	sldx: read	Source GPR.
RA	sldx: write	Source GPR (r0–r31).
CR	sldx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

sldx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• sldx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

n <- (RB)[57:63]
RA <- ((RS) << n)                       if n < 64 else 0

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

sldx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="sldx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:1122
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:65
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:759
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:676-683

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::sldx => {
            let sh = ctx.gpr[instr.rb()] & 0x7F;
            ctx.gpr[instr.ra()] = if sh < 64 {
                ctx.gpr[instr.rs()] << sh
            } else { 0 };
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• 64-bit logical left shift. RA ← RS << (RB & 0x7F) if the shift count is < 64, otherwise RA = 0. Bits shifted past bit 0 are discarded.
• Critical: shift count is 7 bits, not 6. PowerISA reads RB[57:63] (7 bits, 0..127). Counts in [64, 127] produce zero, not RS << (count mod 64). Xenia respects this with & 0x7F and an explicit if sh < 64 check (interpreter.rs:464). C semantics' undefined behaviour for << with a count >= width is a spec-violation source if you naïvely translate.
• No XER[CA] produced by left shifts. Logical right srdx and arithmetic right sradx differ here — arithmetic right does set CA.
• Rc=1 CR0 is correctly 64-bit. interpreter.rs:467 uses as i64 directly. CR0 reflects the sign of the full 64-bit shifted value (which is 0 for shifts ≥ 64, otherwise either LT/GT/EQ).
• Strength-reduced from mulli for power-of-two multipliers.
• No OE bit.

Related Instructions

• slwx — 32-bit logical left shift.
• srdx — 64-bit logical right shift.
• sradx, sradix — 64-bit arithmetic right shifts.
• rldicrx — sldi simplified mnemonic uses this.
• mulli — for non-power-of-two multipliers.

IBM Reference

• AIX 7.3 — sld (Shift Left Doubleword)