xenia-rs/migration/project-root/ppc-manual/alu/slwx.md

slwx — Shift Left Word

Category: Integer ALU · Form: X · Opcode: 0x7c000030

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
slw	slwx	—	Shift Left Word
slw.	slwx	Rc=1	Shift Left Word

Syntax

slw[Rc] [RA], [RS], [RB]

Encoding

slwx — form X

• Opcode word: 0x7c000030
• Primary opcode (bits 0–5): 31
• Extended opcode: 24
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	slwx: read	Source GPR (alias for RD in some stores).
RB	slwx: read	Source GPR.
RA	slwx: write	Source GPR (r0–r31).
CR	slwx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

slwx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• slwx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

n <- (RB)[58:63]
RA <- ((RS) << n) & 0x0000_0000_FFFF_FFFF if n < 32 else 0

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

slwx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="slwx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:1141
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:65
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:757
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:622-631

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::slwx => {
            // PPCBUG-044: 32-bit ABI CR0 view. A result with bit 31 set
            // (e.g. 0x80000000) is negative in i32 view but positive in i64.
            let sh = ctx.gpr[instr.rb()] as u32;
            ctx.gpr[instr.ra()] = if sh < 32 {
                ((ctx.gpr[instr.rs()] as u32) << sh) as u64
            } else { 0 };
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• 32-bit logical left shift, zero-extended to 64. RA ← (RS[32:63] << (RB & 0x3F))[32:63] if (RB & 0x3F) < 32, else RA = 0. The high 32 bits of RA are always zero (zero-extension of the 32-bit result).
• Shift count is 6 bits, RB[58:63] — not 7 like sldx. Counts in [32, 63] produce zero. Xenia reads the full register but the explicit if sh < 32 guard in interpreter.rs:417 prevents Rust UB.
• Spec quirk worth flagging: xenia reads ctx.gpr[instr.rb()] as u32, which uses the low 32 bits of RB, not the spec's RB & 0x3F. For ordinary code these agree (counts ≤ 63), but a maliciously high RB could in principle differ. In practice this is a non-issue.
• No XER[CA] for left shifts.
• Rc=1 CR0 update truncates to 32 bits (interpreter.rs:420). Since the high 32 bits are zero, this matches spec exactly.
• No OE bit.

Related Instructions

• sldx — 64-bit logical left shift.
• srwx, srawx, srawix — 32-bit right shifts.
• rlwinmx — slwi simplified mnemonic uses this.

IBM Reference

• AIX 7.3 — slw (Shift Left Word)