xenia-rs/migration/project-root/ppc-manual/memory/dcbst.md

dcbst — Data Cache Block Store

Category: Memory · Form: X · Opcode: 0x7c00006c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
dcbst	dcbst	—	Data Cache Block Store

Syntax

dcbst [RA0], [RB]

Encoding

dcbst — form X

• Opcode word: 0x7c00006c
• Primary opcode (bits 0–5): 31
• Extended opcode: 54
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	dcbst: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	dcbst: read	Source GPR.

Register Effects

dcbst

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

dcbst

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="dcbst"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:1134
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:19
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:765

Special Cases & Edge Conditions

• Write-through, no invalidate. If the addressed line is dirty, it is written back to memory; the line itself remains in the cache (clean afterwards). Lighter than dcbf — the cache stays warm.
• Cache line size. Xenon's line is 128 bytes; the low seven bits of EA are ignored. There is no dcbst128; the operation is sized to the architectural line.
• RA0 semantics. RA = 0 selects literal zero as base. dcbst 0, RB pushes the line containing address RB to memory.
• Self-modifying code stage 1. The canonical "patch then run" sequence is stw (modify) → dcbst (push dirty data to memory) → sync → icbi (invalidate I-cache for the same address) → isync. dcbst is preferred over dcbf here because it leaves the data in D-cache for any subsequent normal reads.
• DMA hand-off. Used before initiating a GPU or DMA read of a buffer the CPU has just written, to ensure memory holds the latest data.
• Unprivileged. Available from problem state.
• Xenia models as no-op. No cache state is simulated; PC advances and memory is already authoritative.

Related Instructions

• dcbf — flush + invalidate (heavier alternative).
• dcbi — invalidate without write-back (privileged).
• dcbz, dcbz128 — allocate-and-zero.
• dcbt, dcbtst — prefetch hints.
• icbi — instruction-cache invalidate, sequenced after dcbst in self-modifying-code recipes.
• sync, isync — ordering primitives that bracket cache control.

IBM Reference

• AIX 7.3 — dcbst (Data Cache Block Store)
• PowerISA v2.07B Book II § "Storage Control Instructions".