xenia-rs/migration/project-root/ppc-manual/memory/dcbz.md

dcbz — Data Cache Block Clear to Zero

Category: Memory · Form: DCBZ · Opcode: 0x7c0007ec

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
dcbz	dcbz	—	Data Cache Block Clear to Zero
dcbz128	dcbz128	—	Data Cache Block Clear to Zero 128

Syntax

dcbz [RA0], [RB]
dcbz128 [RA0], [RB]

Encoding

dcbz — form DCBZ

• Opcode word: 0x7c0007ec
• Primary opcode (bits 0–5): 31
• Extended opcode: 1014
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	—	reserved
11–15	RA	base register (0 ⇒ literal 0)
16–20	RB	offset register
21–30	XO	extended opcode (1014 for dcbz / 1010 for dcbz128)
31	—	reserved

dcbz128 — form DCBZ

• Opcode word: 0x7c2007ec
• Primary opcode (bits 0–5): 31
• Extended opcode: 1014
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	—	reserved
11–15	RA	base register (0 ⇒ literal 0)
16–20	RB	offset register
21–30	XO	extended opcode (1014 for dcbz / 1010 for dcbz128)
31	—	reserved

Operands

Field	Role	Description
RA0	dcbz: read; dcbz128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	dcbz: read; dcbz128: read	Source GPR.

Register Effects

dcbz

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

dcbz128

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

dcbz

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="dcbz"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:1159
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:19
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:886
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1694-1705

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::dcbz => {
            // Zero 32 bytes at effective address
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = (ea.wrapping_add(ctx.gpr[instr.rb()]) as u32) & !31;
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            for i in 0..8 {
                mem.write_u32(ea + i * 4, 0);
            }
            ctx.pc += 4;
        }

dcbz128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="dcbz128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:1171
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:19
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:887
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1706-1717

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::dcbz128 => {
            // Zero 128 bytes
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = (ea.wrapping_add(ctx.gpr[instr.rb()]) as u32) & !127;
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            for i in 0..32 {
                mem.write_u32(ea + i * 4, 0);
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Cache-line size mismatch. Stock PowerPC dcbz zeroes one architectural cache line — 32 bytes on classic POWER, but the Xenon's L1 line is 128 bytes. Microsoft added dcbz128 (encoded with bit-9 set so RT field reads as 1) to clear a true Xenon line in one instruction. Most Xbox 360 code therefore emits dcbz128; a stray dcbz only zeroes 32 bytes and silently leaves the rest of the line uncleared.
• Alignment is forced via mask. The effective address is masked by ~31 (dcbz) or ~127 (dcbz128) before writing — the low bits are dropped, not validated. Calling dcbz r0, r3 with r3 = 0x10037 writes zeros to 0x10000..0x1007F, not 0x10037..0x100B6.
• No memory read; pure write. Real hardware allocates the line in cache and may skip a read-from-memory fill ("cache-line zero" optimisation). Xenia simulates the architectural effect — 32 (or 128) bytes of zero in target memory — without modelling cache state.
• RA0 semantics. RA = 0 selects literal zero as the base, so dcbz128 0, RB zeros the line containing address RB. The update form does not exist for cache-control instructions.
• Block-fill idiom. Compilers and hand-written copy loops pair dcbz128 with stvx / stw sequences to avoid the cache-line read-allocate that a cold store would trigger. Skipping the read is the entire point.
• Privilege. dcbz is unprivileged (problem-state); does not require supervisor mode. It can fault on protection or unmapped memory like an ordinary store.
• Sequencing. Not synchronising. Pair with sync / lwsync when the zeros must be visible before subsequent loads on another thread.

Related Instructions

• dcbf — flush a line back to memory.
• dcbst — store-through (write-back without invalidate).
• dcbi — invalidate (privileged on most cores).
• dcbt, dcbtst — touch / touch-for-store hints.
• icbi — instruction-cache invalidate (companion to data-cache control).
• stvx, stw — typical pair-mates in block-fill loops.

IBM Reference

• AIX 7.3 — dcbz (Data Cache Block Set to Zero)
• Microsoft Xbox 360 XDK / Xenon Programming Guide — for dcbz128 specifics; PowerISA v2.07B Book II § "Storage Control Instructions" for the architectural baseline.