xenia-rs/migration/project-root/ppc-manual/memory/stdcx.md

stdcx — Store Doubleword Conditional Indexed

Category: Memory · Form: X · Opcode: 0x7c0001ad

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stdcx	stdcx	—	Store Doubleword Conditional Indexed

Syntax

stdcx. [RS], [RA0], [RB]

Encoding

stdcx — form X

• Opcode word: 0x7c0001ad
• Primary opcode (bits 0–5): 31
• Extended opcode: 214
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	stdcx: read	Source GPR (alias for RD in some stores).
RA0	stdcx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stdcx: read	Source GPR.
CR	stdcx: write	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

stdcx

• Reads (always): RS, RA0, RB
• Reads (conditional): none
• Writes (always): CR
• Writes (conditional): none

Status-Register Effects

• stdcx: CR0 ← signed-compare(result, 0) with SO ← XER[SO] (always).

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stdcx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stdcx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:827
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:69
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:789
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4576-4626

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stdcx => {
            let ea = ea_indexed(ctx, instr);
            let line = ea & !RESERVATION_MASK;
            let table_route = ctx
                .reservation_table
                .as_ref()
                .filter(|t| t.is_enabled())
                .cloned();
            // PPCBUG-151: stdcx. requires a doubleword (ldarx) reservation;
            // a word (lwarx) reservation must not commit here.
            let width_ok = ctx.reservation_width == 8;
            let success = if let Some(t) = &table_route {
                ctx.has_reservation
                    && width_ok
                    && ctx.reserved_line == line
                    && t.try_commit(ea, ctx.reserved_generation, ctx.hw_id)
            } else {
                // Legacy per-ctx path (M2 default / lockstep).
                // PPCBUG-108: same sentinel as stwcx. — fires on non-primary
                // HW slots if the table is disabled under --parallel.
                debug_assert!(
                    ctx.hw_id == 0,
                    "PPCBUG-108: legacy per-ctx stdcx. on non-primary HW slot \
                     (hw_id={}) — ReservationTable must be enabled under --parallel",
                    ctx.hw_id
                );
                ctx.has_reservation && width_ok && ctx.reserved_line == line
            };
            if success {
                mem.write_u64(ea, ctx.gpr[instr.rs()]);
                ctx.cr[0] = crate::context::CrField {
                    lt: false,
                    gt: false,
                    eq: true,
                    so: ctx.xer_so != 0,
                };
            } else {
                ctx.cr[0] = crate::context::CrField {
                    lt: false,
                    gt: false,
                    eq: false,
                    so: ctx.xer_so != 0,
                };
                if let Some(t) = &table_route {
                    t.release(ea, ctx.reserved_generation, ctx.hw_id);
                }
            }
            ctx.has_reservation = false;
            ctx.reservation_width = 0; // PPCBUG-151: always clear on exit
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Always sets Rc=1 (the trailing dot). The mnemonic is stdcx. — there is no non-Rc variant. CR0 is updated unconditionally to communicate success/failure. EQ=1 means the conditional store succeeded; EQ=0 means it failed (the prior reservation was cleared and no memory was written).
• Reservation check. Xenia's snapshot tests has_reservation && reserved_addr == ea. On match it performs mem.write_u64, sets EQ=1. On mismatch it leaves memory untouched and sets EQ=0. In both cases the reservation is cleared (has_reservation = false), so a retry must be preceded by a fresh ldarx.
• Hardware granule. PowerISA defines reservation by aligned doubleword; Xenon implementations widen this to one 128-byte cache line. A store by another agent anywhere in the line clears the reservation. Xenia's per-address check is more permissive than hardware.
• Alignment requirement. EA must be 8-byte aligned. Unaligned stdcx. raises an alignment exception on real hardware.
• RA0 semantics. When RA = 0, base is literal zero — stdcx. RS, 0, RB writes at exact RB.
• CR0[SO] reflects XER[SO]. Like all CR-updating ops, CR0[SO] is copied from XER[SO] rather than computed from this instruction.
• Spurious failures permitted. Hardware may report failure even when no actual conflict occurred (e.g. on context switch). Application code treats failure as a normal retry condition.
• Pair atomically with ldarx. Don't interleave loads/stores between the pair; an lwsync inside the loop body is common.

Related Instructions

• ldarx — load-and-reserve doubleword (the matching load).
• stwcx / lwarx — 32-bit reservation pair.
• std, stdx — non-conditional doubleword stores.
• sync, lwsync, isync — barriers used around reservation pairs.

IBM Reference

• AIX 7.3 — stdcx. (Store Doubleword Conditional Indexed)
• PowerISA v2.07B Book II § "Atomic Update Primitives" for canonical reservation semantics and granule rules.