xenia-rs/migration/project-root/ppc-manual/memory/std.md

std — Store Doubleword

Category: Memory · Form: DS · Opcode: 0xf8000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
std	std	—	Store Doubleword
stdu	stdu	—	Store Doubleword with Update
stdux	stdux	—	Store Doubleword with Update Indexed
stdx	stdx	—	Store Doubleword Indexed

Syntax

std [RS], [ds]([RA0])
stdu [RS], [ds]([RA])
stdux [RS], [RA], [RB]
stdx [RS], [RA0], [RB]

Encoding

std — form DS

• Opcode word: 0xf8000000
• Primary opcode (bits 0–5): 62
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS)
11–15	RA	source GPR (0 ⇒ literal 0)
16–29	DS	14-bit signed word-scaled displacement
30–31	XO	extended opcode

stdu — form DS

• Opcode word: 0xf8000001
• Primary opcode (bits 0–5): 62
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS)
11–15	RA	source GPR (0 ⇒ literal 0)
16–29	DS	14-bit signed word-scaled displacement
30–31	XO	extended opcode

stdux — form X

• Opcode word: 0x7c00016a
• Primary opcode (bits 0–5): 31
• Extended opcode: 181
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

stdx — form X

• Opcode word: 0x7c00012a
• Primary opcode (bits 0–5): 31
• Extended opcode: 149
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	std: read; stdu: read; stdux: read; stdx: read	Source GPR (alias for RD in some stores).
RA	std: read; stdu: read; stdu: write; stdux: read; stdux: write	Source GPR (r0–r31).
ds	std: read; stdu: read	14-bit signed word-aligned displacement (DS << 2).
RB	stdux: read; stdx: read	Source GPR.
RA0	stdx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.

Register Effects

std

• Reads (always): RS, RA, ds
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

stdu

• Reads (always): RS, RA, ds
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

stdux

• Reads (always): RS, RA, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

stdx

• Reads (always): RS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

EA <- (RA|0) + EXTS(ds || 0b00)
MEM(EA, 8) <- (RS)

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

std

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="std"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:575
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:69
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:399
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1399-1407

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::std => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(instr.ds() as i64 as u64) as u32;
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            mem.write_u64(ea, ctx.gpr[instr.rs()]);
            ctx.pc += 4;
        }

stdu

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stdu"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:594
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:69
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:400
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1417-1425

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stdu => {
            let ea = ctx.gpr[instr.ra()].wrapping_add(instr.ds() as i64 as u64) as u32;
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            mem.write_u64(ea, ctx.gpr[instr.rs()]);
            ctx.gpr[instr.ra()] = ea as u64;
            ctx.pc += 4;
        }

stdux

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stdux"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:604
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:69
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:786
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1426-1434

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stdux => {
            let ea = ctx.gpr[instr.ra()].wrapping_add(ctx.gpr[instr.rb()]) as u32;
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            mem.write_u64(ea, ctx.gpr[instr.rs()]);
            ctx.gpr[instr.ra()] = ea as u64;
            ctx.pc += 4;
        }

stdx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stdx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:614
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:69
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:781
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1408-1416

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stdx => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            mem.write_u64(ea, ctx.gpr[instr.rs()]);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• DS-form, not D-form. Like ld, std uses a 14-bit signed displacement scaled by 4 (EXTS(ds || 0b00)). Bits 30–31 are the extended opcode used to distinguish std (XO=0) from stdu (XO=1). Assemblers verify the byte displacement is a multiple of 4.
• Big-endian write. The 64-bit value of RS is written most-significant-byte-first: RS[0:7] to EA, RS[56:63] to EA+7. Xenia's mem.write_u64 performs the host-side byte swap if needed.
• RA0 for std and stdx. When RA = 0, base is the literal zero. Update forms stdu / stdux invoke RA = 0 as an invalid form (no RA = RS collision possible — RS and RA are independent encoding fields, and even if equal the store reads RS first).
• Update-form post-write. stdu / stdux write EA to RA after the store. Order is store-then-update.
• Alignment. Xenon tolerates unaligned doubleword stores. PowerISA permits implementations to raise alignment exceptions; portable code keeps doublewords 8-byte aligned. Cache-inhibited storage may force alignment.
• Cache-line behaviour. A doubleword store fits inside one Xenon cache line (128 B), so it's a single line write. A doubleword store that straddles a line boundary triggers two line accesses — keep doublewords 8-byte aligned to avoid the cost.
• 64-bit pointer / counter stores. Xbox 360 user code is 32-bit, but kernel structures, TOC entries, and 64-bit counters are stored with std.

Related Instructions

• stw, sth, stb — narrower integer stores.
• stdbrx — byte-reversed doubleword store.
• stdcx — store-conditional (the doubleword reservation pair end).
• ld, ldu, ldx, ldux — corresponding loads.
• stfd — FP doubleword store (same width, different register file).

IBM Reference

• AIX 7.3 — std (Store Doubleword)
• AIX 7.3 — stdu / stdx / stdux