xenia-rs/migration/project-root/ppc-manual/memory/sthbrx.md

sthbrx — Store Half Word Byte-Reverse Indexed

Category: Memory · Form: X · Opcode: 0x7c00072c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
sthbrx	sthbrx	—	Store Half Word Byte-Reverse Indexed

Syntax

sthbrx [RS], [RA0], [RB]

Encoding

sthbrx — form X

• Opcode word: 0x7c00072c
• Primary opcode (bits 0–5): 31
• Extended opcode: 918
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	sthbrx: read	Source GPR (alias for RD in some stores).
RA0	sthbrx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	sthbrx: read	Source GPR.

Register Effects

sthbrx

• Reads (always): RS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

sthbrx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="sthbrx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:667
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:73
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:846
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1822-1830

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::sthbrx => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() { t.invalidate_for_write(ea); }
            }
            mem.write_u16(ea, (ctx.gpr[instr.rs()] as u16).swap_bytes());
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Writes little-endian half. Takes the low 16 bits of RS, swaps the two bytes, writes them at EA. After execution, byte at EA is RS[56:63] (low byte) and byte at EA+1 is RS[48:55] (high byte). The xenia snapshot does (ctx.gpr[instr.rs()] as u16).swap_bytes().
• Used to emit little-endian half-words. Symmetric counterpart of lhbrx. Common in PNG / ZIP / RIFF chunk emit paths.
• High bits of RS ignored. Storing a 64-bit value through sthbrx truncates and reverses only the low half-word; the high 48 bits are not consulted.
• X-form only — no D-form, no update form. Only the indexed form exists. EA = (RA|0) + RB.
• RA0 semantics. When RA = 0, base is literal zero; sthbrx RS, 0, RB writes at exact RB.
• Alignment. Hardware tolerates unaligned half-word writes; cache-inhibited storage may raise alignment exceptions on real hardware.
• No CR / FPSCR effects.

Related Instructions

• lhbrx — load-half byte-reverse (matching load).
• stwbrx, stdbrx — wider byte-reverse stores.
• sth, sthx — non-reversing half stores.

IBM Reference

• AIX 7.3 — sthbrx (Store Half Byte-Reverse Indexed)
• PowerISA v2.07B Book II § "Byte-Reverse Storage Access".