xenia-rs/migration/project-root/ppc-manual/memory/stvlxl.md

stvlxl — Store Vector Left Indexed LRU

Category: Memory · Form: X · Opcode: 0x7c00070e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stvlxl	stvlxl	—	Store Vector Left Indexed LRU
stvlxl128	stvlxl128	—	Store Vector Left Indexed LRU 128

Syntax

stvlxl [VS], [RA0], [RB]
stvlxl128 [VS], [RA0], [RB]

Encoding

stvlxl — form X

• Opcode word: 0x7c00070e
• Primary opcode (bits 0–5): 31
• Extended opcode: 903
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

stvlxl128 — form VX128_1

• Opcode word: 0x10000703
• Primary opcode (bits 0–5): 4
• Extended opcode: 1795
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
VS	stvlxl: read; stvlxl128: read	Source vector register (alias for VD on stores).
RA0	stvlxl: read; stvlxl128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stvlxl: read; stvlxl128: read	Source GPR.

Register Effects

stvlxl

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

stvlxl128

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stvlxl

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stvlxl"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:271
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:77
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:845
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3103-3119

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stvlx | PpcOpcode::stvlxl => {
            let ea = ea_indexed(ctx, instr);
            // PPCBUG-513: stvlx/stvlxl were missing invalidate_for_write.
            // store_vector_left writes [ea, (ea & !0xF)+15]; in the worst case (ea & 0xF == 0)
            // that is exactly 16 bytes all within the same 16-byte block, so ea+15 lands in the
            // same 128-byte cache line. Two-call form is kept for defensive correctness.
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() {
                    let first_line = ea & !RESERVATION_MASK;
                    let last_line = ea.wrapping_add(15) & !RESERVATION_MASK;
                    t.invalidate_for_write(first_line);
                    if last_line != first_line { t.invalidate_for_write(last_line); }
                }
            }
            crate::vmx::store_vector_left(mem, ea, ctx.vr[instr.rs()]);
            ctx.pc += 4;
        }

stvlxl128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="stvlxl128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:274
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:77
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:426
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3120-3133

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::stvlx128 | PpcOpcode::stvlxl128 => {
            let ea = ea_indexed(ctx, instr);
            // PPCBUG-513: stvlx128/stvlxl128 were missing invalidate_for_write.
            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
                if t.has_active_reservers() {
                    let first_line = ea & !RESERVATION_MASK;
                    let last_line = ea.wrapping_add(15) & !RESERVATION_MASK;
                    t.invalidate_for_write(first_line);
                    if last_line != first_line { t.invalidate_for_write(last_line); }
                }
            }
            crate::vmx::store_vector_left(mem, ea, ctx.vr[instr.vs128()]);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Same data effect as stvlx, with LRU cache hint. Writes (16 - (EA mod 16)) bytes from the left half of VS starting at EA; right half not stored. The l suffix marks the touched line as least-recently-used.
• Hint ignored under emulation. Xenia's snapshot is shared with stvlx (PpcOpcode::stvlx | PpcOpcode::stvlxl => …).
• No alignment masking. The exact EA controls how data is split.
• RA0 semantics. RA = 0 selects literal zero.
• Microsoft Xbox 360 specific. Part of VMX128 / Cell BE.
• Streaming write use case. Pair with stvrxl when the buffer is one-pass output that should not pollute the cache.
• VMX128 sibling (stvlxl128). Identical semantics; alternative operand encoding addressing v0..v127.

Related Instructions

• stvlx, stvlx128 — non-hint variants.
• stvrxl, stvrxl128 — store-right LRU partner.
• stvxl, stvxl128 — aligned LRU vector store.
• lvlxl, lvrxl — symmetric LRU loads.

IBM Reference

• AIX 7.3 — stvlxl (Store Vector Left Indexed Last)
• PowerISA v2.07B Book I "Vector Facility"; Microsoft Xbox 360 XDK for cache-hint behaviour.