xenia-rs/migration/project-root/ppc-manual/vmx/vaddsws.md

vaddsws — Vector Add Signed Word Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000380

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vaddsws	vaddsws	—	Vector Add Signed Word Saturate

Syntax

vaddsws [VD], [VA], [VB]

Encoding

vaddsws — form VX

• Opcode word: 0x10000380
• Primary opcode (bits 0–5): 4
• Extended opcode: 896
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vaddsws: read	Source A vector register.
VB	vaddsws: read	Source B vector register.
VD	vaddsws: write	Destination vector register.
VSCR	vaddsws: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vaddsws

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vaddsws: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vaddsws

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vaddsws"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:364
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:89
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:512
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3354-3365

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vaddsws => {
            let a = crate::vmx::as_i32x4(ctx.vr[instr.ra()]);
            let b = crate::vmx::as_i32x4(ctx.vr[instr.rb()]);
            let mut r = [0i32; 4]; let mut sat = false;
            for i in 0..4 {
                let (v, s) = crate::vmx::sat_add_i32(a[i], b[i]);
                r[i] = v; sat |= s;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = crate::vmx::from_i32x4(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Four signed-word lanes, saturating. Each VD[i] = clamp(VA[i] + VB[i], INT32_MIN, INT32_MAX) for i = 0..3. Lane 0 (VD[0..3] after stvx) is the most-significant word.
• VSCR[SAT] is sticky-set if any lane clamps. Xenia tracks this through crate::vmx::sat_add_i32 (crates/xenia-cpu/src/vmx.rs) and ORs the flag into the architectural VSCR[SAT].
• No multi-precision carry. Unlike vaddcuw, vaddsws does not expose a per-lane carry/borrow — a saturated lane simply clips; it does not overflow into the adjacent lane.
• Asymmetric clamp. INT32_MAX + 1 = INT32_MAX; INT32_MIN + (-1) = INT32_MIN.
• The modulo sibling is vadduwm. Modulo add for signed and unsigned words is bit-identical; switch to vaddsws only when clipping with sign awareness is desired.
• No XER side effects.
• No VMX128 sibling.
• Common usage. Accumulate four 32-bit signed sums per cycle (e.g. dot products of int16 lanes after a vmsumshs — which already saturates internally — for further accumulation across multiple iterations).

Related Instructions

• vadduws — same width, unsigned saturating add.
• vadduwm — same width, modulo (non-saturating) add; sign-agnostic.
• vaddsbs, vaddshs — signed saturating add at byte / half width.
• vsubsws — the matching signed saturating subtract.
• vmsumshs, vmsumuhs — saturating multiply-sum that often feeds a vaddsws chain.
• mtvscr / mfvscr — read or clear the VSCR[SAT] bit.

IBM Reference

• AIX 7.3 — vaddsws (Vector Add Signed Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Saturating Integer Arithmetic