xenia-rs/migration/project-root/ppc-manual/vmx/vaddshs.md

vaddshs — Vector Add Signed Half Word Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000340

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vaddshs	vaddshs	—	Vector Add Signed Half Word Saturate

Syntax

vaddshs [VD], [VA], [VB]

Encoding

vaddshs — form VX

• Opcode word: 0x10000340
• Primary opcode (bits 0–5): 4
• Extended opcode: 832
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vaddshs: read	Source A vector register.
VB	vaddshs: read	Source B vector register.
VD	vaddshs: write	Destination vector register.
VSCR	vaddshs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vaddshs

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vaddshs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vaddshs

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vaddshs"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:356
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:89
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:505
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3306-3317

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vaddshs => {
            let a = crate::vmx::as_i16x8(ctx.vr[instr.ra()]);
            let b = crate::vmx::as_i16x8(ctx.vr[instr.rb()]);
            let mut r = [0i16; 8]; let mut sat = false;
            for i in 0..8 {
                let (v, s) = crate::vmx::sat_add_i16(a[i], b[i]);
                r[i] = v; sat |= s;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = crate::vmx::from_i16x8(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Eight signed-half lanes, saturating. Each VD[i] = clamp(VA[i] + VB[i], -32768, +32767) for i = 0..7, with both inputs interpreted as signed int16. Lane 0 (VD[0..1] after stvx) is the most-significant half.
• VSCR[SAT] is sticky-set if any lane clamps. Once set, it stays set until explicit clear via mtvscr. Xenia uses crate::vmx::sat_add_i16 (crates/xenia-cpu/src/vmx.rs) which returns the per-lane saturation flag; the OR is written back via ctx.set_vscr_sat(true).
• The modulo counterpart is vadduhm. Modulo add for signed and unsigned halves is bit-identical, so vadduhm covers both when wraparound is wanted; switch to vaddshs only when clipping with sign awareness is desired.
• Asymmetric clamp. +32767 + 1 = +32767; -32768 + (-1) = -32768.
• Common 16-bit DSP idiom. Audio mixing and fixed-point colour blending lean heavily on vaddshs to combine signed Q15 / Q1.15 quantities without wraparound artefacts.
• No XER side effects, no NJ involvement (this is an integer op).
• No VMX128 sibling.

Related Instructions

• vadduhs — same width, unsigned saturating add (clamps to 0..0xFFFF).
• vadduhm — same width, modulo add; sign-agnostic.
• vaddsbs, vaddsws — signed saturating add at byte / word width.
• vsubshs — the matching signed saturating subtract.
• vmhaddshs, vmhraddshs — signed-half multiply-add with saturation, common for fixed-point DSP.
• mtvscr / mfvscr — read or clear the VSCR[SAT] bit affected here.

IBM Reference

• AIX 7.3 — vaddshs (Vector Add Signed Half Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Saturating Integer Arithmetic