xenia-rs/migration/project-root/ppc-manual/vmx/vaddubm.md

vaddubm — Vector Add Unsigned Byte Modulo

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vaddubm	vaddubm	—	Vector Add Unsigned Byte Modulo

Syntax

vaddubm [VD], [VA], [VB]

Encoding

vaddubm — form VX

• Opcode word: 0x10000000
• Primary opcode (bits 0–5): 4
• Extended opcode: 0
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vaddubm: read	Source A vector register.
VB	vaddubm: read	Source B vector register.
VD	vaddubm: write	Destination vector register.

Register Effects

vaddubm

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vaddubm

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vaddubm"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:372
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:90
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:434
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3198-3205

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vaddubm => {
            let a = ctx.vr[instr.ra()].as_bytes();
            let b = ctx.vr[instr.rb()].as_bytes();
            let mut r = [0u8; 16];
            for i in 0..16 { r[i] = a[i].wrapping_add(b[i]); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_bytes(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Sixteen independent byte lanes. VD[i] = (VA[i] + VB[i]) mod 256 for i = 0..15. Lane 0 is the most-significant byte (the byte at the lowest address after stvx).
• Modulo wrap, not saturating. Overflow silently wraps in 8-bit unsigned arithmetic — there is no carry-out and VSCR[SAT] is not touched. This is the same bit pattern as a signed-byte modulo add, so vaddubm is also the de-facto vaddsbm (which doesn't exist in the ISA — modulo arithmetic is sign-agnostic).
• No carry, no flags. XER is untouched (Altivec never updates XER[CA]/XER[OV]). The dedicated vaddcuw instruction exists only because there is no SAT/CA byproduct — extracting the carry needs an explicit op.
• Aliasing is legal. vaddubm v3, v3, v4 (in-place accumulate) is a single-cycle issue on Xenon's VMX pipe.
• VSCR untouched. Neither SAT nor NJ is read or written. Schedulable next to floats, compares and saturating ops without dependency stalls.
• Pairs with a saturating sibling. When you need 8-bit add with clamping, switch to vaddubs (unsigned saturate, range 0..0xFF) or vaddsbs (signed saturate, range -128..+127) — both of which do sticky-set VSCR[SAT].
• No VMX128 sibling. The vaddubm opcode is not exposed as a *128 form; the 32-register encoding is the only one available.

Related Instructions

• vaddubs — same lane width, unsigned saturating add (SAT sticky-set on overflow).
• vaddsbs — same lane width, signed saturating add.
• vadduhm, vadduwm — modulo add with 8-lane half / 4-lane word width.
• vaddcuw — produces the per-lane carry bits a 32-bit modulo add discards.
• vsububm — the matching modulo subtract.
• vavgub — unsigned byte average (carry-aware: (a + b + 1) >> 1), useful when byte addition needs rounding without overflow.

IBM Reference

• AIX 7.3 — vaddubm (Vector Add Unsigned Byte Modulo)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Integer Arithmetic