xenia-rs/migration/project-root/ppc-manual/vmx/vadduhm.md

vadduhm — Vector Add Unsigned Half Word Modulo

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000040

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vadduhm	vadduhm	—	Vector Add Unsigned Half Word Modulo

Syntax

vadduhm [VD], [VA], [VB]

Encoding

vadduhm — form VX

• Opcode word: 0x10000040
• Primary opcode (bits 0–5): 4
• Extended opcode: 64
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vadduhm: read	Source A vector register.
VB	vadduhm: read	Source B vector register.
VD	vadduhm: write	Destination vector register.

Register Effects

vadduhm

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vadduhm

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vadduhm"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:387
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:90
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:441
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3214-3221

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vadduhm => {
            let a = ctx.vr[instr.ra()].as_u16x8();
            let b = ctx.vr[instr.rb()].as_u16x8();
            let mut r = [0u16; 8];
            for i in 0..8 { r[i] = a[i].wrapping_add(b[i]); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u16x8_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Eight half-word lanes. VD[i] = (VA[i] + VB[i]) mod 65536 for i = 0..7. Lane 0 (VD[0..1] after stvx) is the most-significant half.
• Modulo wrap, not saturating. Overflow silently wraps in 16-bit arithmetic; VSCR[SAT] is not touched and there is no carry-out. Sign-agnostic — modulo add for signed int16 and unsigned u16 is bit-pattern-identical, so this is also the de-facto vaddshm.
• No XER, no NJ involvement.
• Aliasing legal. vadduhm v3, v3, v4 is a single-issue accumulate.
• Pairs with saturating siblings. Switch to vadduhs for unsigned clamp at 0xFFFF or vaddshs for signed clamp at ±32767 when overflow needs to be detected via sticky VSCR[SAT].
• Common usage. Multi-precision adds composed from 16-bit lanes; UV-coordinate accumulation; per-pixel half-precision counters.
• No VMX128 sibling.

Related Instructions

• vadduhs — same width, unsigned saturating add.
• vaddshs — same width, signed saturating add.
• vaddubm, vadduwm — modulo add at byte / word width.
• vsubuhm — the matching modulo subtract.
• vavguh — unsigned half-word rounding average; useful when addition needs to stay representable.

IBM Reference

• AIX 7.3 — vadduhm (Vector Add Unsigned Half Word Modulo)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Integer Arithmetic