xenia-rs/migration/project-root/ppc-manual/vmx/vcmpgtuh.md

vcmpgtuh — Vector Compare Greater-Than Unsigned Half Word

Category: VMX (Altivec) · Form: VC · Opcode: 0x10000246

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vcmpgtuh	vcmpgtuh	—	Vector Compare Greater-Than Unsigned Half Word
vcmpgtuh.	vcmpgtuh	Rc=1	Vector Compare Greater-Than Unsigned Half Word

Syntax

vcmpgtuh[Rc] [VD], [VA], [VB]

Encoding

vcmpgtuh — form VC

• Opcode word: 0x10000246
• Primary opcode (bits 0–5): 4
• Extended opcode: 582
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21	Rc	record-form flag (updates CR6)
22–31	XO	extended opcode (10 bits)

Operands

Field	Role	Description
VA	vcmpgtuh: read	Source A vector register.
VB	vcmpgtuh: read	Source B vector register.
VD	vcmpgtuh: write	Destination vector register.
CR	vcmpgtuh: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

vcmpgtuh

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): CR

Status-Register Effects

• vcmpgtuh: CR6 ← [all-true, 0, all-false, 0] when Rc=1.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vcmpgtuh

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vcmpgtuh"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:751
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:97
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:563
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3775-3787

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vcmpgtuh => {
            let a = ctx.vr[instr.ra()].as_u16x8();
            let b = ctx.vr[instr.rb()].as_u16x8();
            let mut r = [0u16; 8];
            for i in 0..8 { r[i] = if a[i] > b[i] { 0xFFFF } else { 0 }; }
            let v = xenia_types::Vec128::from_u16x8_array(r);
            if instr.vc_rc_bit() {
                let (t, f) = crate::vmx::cr6_flags_from_mask(v);
                ctx.cr[6] = crate::context::CrField { lt: t, gt: false, eq: f, so: false };
            }
            ctx.vr[instr.rd()] = v;
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Per-half mask: all-ones / all-zero. Eight half-word lanes; VD[i] = (uint16(VA[i]) > uint16(VB[i])) ? 0xFFFF : 0x0000. Lane 0 is the most-significant half.
• Sign matters. 0xFFFF > 0x0001 is true unsigned but false signed (-1 > 1).
• CR6 update when Rc=1 (vcmpgtuh.). CR6 = [lt = all-true, gt = 0, eq = all-false, so = 0].
• Compose with vsel. Mask drives vsel per half.
• Common usage. UTF-16 codepoint range testing, unsigned-half threshold binarisation.
• No VSCR interaction, no XER, no traps.
• Aliasing legal.
• No VMX128 sibling.

Related Instructions

• vcmpgtsh — same width, signed >.
• vcmpequh — equality at half width.
• vcmpgtub, vcmpgtuw — unsigned > at byte / word width.
• vsel, vand, vandc, vor, vxor — mask consumers / combinators.
• vmaxuh, vminuh — direct unsigned max / min.

IBM Reference

• AIX 7.3 — vcmpgtuh (Vector Compare Greater-Than Unsigned Half Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Vector Compares