xenia-rs/migration/project-root/ppc-manual/vmx/vpkshus.md

vpkshus — Vector Pack Signed Half Word Unsigned Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000010e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vpkshus	vpkshus	—	Vector Pack Signed Half Word Unsigned Saturate
vpkshus128	vpkshus128	—	Vector128 Pack Signed Half Word Unsigned Saturate

Syntax

vpkshus [VD], [VA], [VB]
vpkshus128 [VD], [VA], [VB]

Encoding

vpkshus — form VX

• Opcode word: 0x1000010e
• Primary opcode (bits 0–5): 4
• Extended opcode: 270
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vpkshus128 — form VX128

• Opcode word: 0x14000240
• Primary opcode (bits 0–5): 5
• Extended opcode: 576
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vpkshus: read; vpkshus128: read	Source A vector register.
VB	vpkshus: read; vpkshus128: read	Source B vector register.
VD	vpkshus: write; vpkshus128: write	Destination vector register.
VSCR	vpkshus: write; vpkshus128: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vpkshus

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

vpkshus128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vpkshus: VSCR[SAT] may be stickied on saturating vector operations.
• vpkshus128: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vpkshus

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vpkshus"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1953
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:113
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:459
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4057-4069

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vpkshus | PpcOpcode::vpkshus128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vpkshus128);
            let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
                               else { (instr.ra(), instr.rb(), instr.rd()) };
            let a = crate::vmx::as_i16x8(ctx.vr[ra]);
            let b = crate::vmx::as_i16x8(ctx.vr[rb]);
            let mut r = [0u8; 16]; let mut sat = false;
            for i in 0..8 { let (v, s) = crate::vmx::sat_i16_to_u8(a[i]); r[i] = v; sat |= s; }
            for i in 0..8 { let (v, s) = crate::vmx::sat_i16_to_u8(b[i]); r[8 + i] = v; sat |= s; }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[rd] = xenia_types::Vec128::from_bytes(r);
            ctx.pc += 4;
        }

vpkshus128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vpkshus128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1956
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:113
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:620
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4057-4069

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vpkshus | PpcOpcode::vpkshus128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vpkshus128);
            let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
                               else { (instr.ra(), instr.rb(), instr.rd()) };
            let a = crate::vmx::as_i16x8(ctx.vr[ra]);
            let b = crate::vmx::as_i16x8(ctx.vr[rb]);
            let mut r = [0u8; 16]; let mut sat = false;
            for i in 0..8 { let (v, s) = crate::vmx::sat_i16_to_u8(a[i]); r[i] = v; sat |= s; }
            for i in 0..8 { let (v, s) = crate::vmx::sat_i16_to_u8(b[i]); r[8 + i] = v; sat |= s; }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[rd] = xenia_types::Vec128::from_bytes(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Signed half-word → unsigned byte saturating pack. Each of the 16 input half-word lanes (8 from VA, 8 from VB) is interpreted as int16 and clamped to [0, 255]. Negative values → 0; values above 255 → 255. Clamping any lane sticky-sets VSCR[SAT].
• Lane-count doubling. 16 half-word lanes → 16 byte lanes, VA filling VD.b[0..7] and VB filling VD.b[8..15].
• Difference from vpkshss. Both take signed half-words; shss clamps to int8, shus clamps to uint8. Choose shus when the signed negative half is not physically meaningful (e.g. after subtracting a clamped-at-zero value).
• VSCR[SAT] is sticky.
• No Rc, no XER / FPSCR.
• VMX128 sibling vpkshus128. Same behaviour with wider register file.

Related Instructions

• vpkshss — signed → signed clamp.
• vpkuhus — unsigned input → unsigned byte.
• vpkuhum — unsigned input, truncating (modulo) pack.
• vpkswus — the word → half-word signed→unsigned analogue.
• vupkhub-family unpacks (if present) — the inverse.

IBM Reference

• AIX 7.3 — vpkshus (Vector Pack Signed Half Word Unsigned Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting