xenia-rs/migration/project-root/ppc-manual/vmx/vrfin.md

vrfin — Vector Round to Floating-Point Integer Nearest

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000020a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vrfin	vrfin	—	Vector Round to Floating-Point Integer Nearest
vrfin128	vrfin128	—	Vector128 Round to Floating-Point Integer Nearest

Syntax

vrfin [VD], [VB]
vrfin128 [VD], [VB]

Encoding

vrfin — form VX

• Opcode word: 0x1000020a
• Primary opcode (bits 0–5): 4
• Extended opcode: 522
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vrfin128 — form VX128_3

• Opcode word: 0x18000370
• Primary opcode (bits 0–5): 6
• Extended opcode: 880
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (6)
6–10	VD128l	destination low 5 bits
11–15	IMM	5-bit immediate
16–20	VB128l	source B low 5 bits
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VB	vrfin: read; vrfin128: read	Source B vector register.
VD	vrfin: write; vrfin128: write	Destination vector register.

Register Effects

vrfin

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vrfin128

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vrfin

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vrfin"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1253
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:118
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:479
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2473-2483

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vrfin | PpcOpcode::vrfin128 => {
            // PPCBUG-432: ISA round-to-nearest-even, NOT Rust's `round()`
            // (which is round-half-away-from-zero).
            let vb = if matches!(instr.opcode, PpcOpcode::vrfin128) { instr.vb128() } else { instr.rb() };
            let vd = if matches!(instr.opcode, PpcOpcode::vrfin128) { instr.vd128() } else { instr.rd() };
            let b = ctx.vr[vb].as_f32x4();
            let mut r = [0f32; 4];
            for i in 0..4 { r[i] = b[i].round_ties_even(); }
            ctx.vr[vd] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }

vrfin128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vrfin128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1256
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:118
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:661
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:2473-2483

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vrfin | PpcOpcode::vrfin128 => {
            // PPCBUG-432: ISA round-to-nearest-even, NOT Rust's `round()`
            // (which is round-half-away-from-zero).
            let vb = if matches!(instr.opcode, PpcOpcode::vrfin128) { instr.vb128() } else { instr.rb() };
            let vd = if matches!(instr.opcode, PpcOpcode::vrfin128) { instr.vd128() } else { instr.rd() };
            let b = ctx.vr[vb].as_f32x4();
            let mut r = [0f32; 4];
            for i in 0..4 { r[i] = b[i].round_ties_even(); }
            ctx.vr[vd] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Round to nearest integer. Each 32-bit float lane of VB is rounded to the nearest representable integer value. Xenia-rs uses Rust's f32::round, which rounds half-away-from-zero; the hardware Xenon actually implements round-ties-to-even. This is a known small mismatch tracked in xenia.
• IEEE-754 binary32 output; VSCR[NJ] honoured.
• Integer-too-big lanes are no-ops (|x| ≥ 2²³).
• NaN and ±∞ pass through unchanged.
• No VSCR[SAT], no FPSCR update.
• Big-endian lane indexing.
• VMX128 sibling vrfin128.

Related Instructions

• vrfim — round toward −∞.
• vrfip — round toward +∞.
• vrfiz — round toward zero.
• vctsxs, vctuxs — float → fixed-point integer.

IBM Reference

• AIX 7.3 — vrfin (Vector Round to Floating-Point Integer to Nearest)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic