xenia-rs/migration/project-root/ppc-manual/vmx/vctuxs.md

vctuxs — Vector Convert to Unsigned Fixed-Point Word Saturate

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000038a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vctuxs	vctuxs	—	Vector Convert to Unsigned Fixed-Point Word Saturate

Syntax

vctuxs [VD], [VB], [UIMM]

Encoding

vctuxs — form VX

• Opcode word: 0x1000038a
• Primary opcode (bits 0–5): 4
• Extended opcode: 906
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VB	vctuxs: read	Source B vector register.
UIMM	vctuxs: read	16-bit unsigned immediate. Zero-extended.
VD	vctuxs: write	Destination vector register.
VSCR	vctuxs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vctuxs

• Reads (always): VB, UIMM
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vctuxs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vctuxs

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vctuxs"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:554
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:98
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:515
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4293-4304

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vctuxs => {
            let uimm = (instr.raw >> 16) & 0x1F;
            let b = ctx.vr[instr.rb()].as_f32x4();
            let mut r = [0u32; 4]; let mut sat = false;
            for i in 0..4 {
                let (v, s) = crate::vmx::cvt_f32_to_u32_sat(b[i], uimm);
                r[i] = v; sat |= s;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Convert IEEE float lane to unsigned-Q uint32, saturating. For each of the four word lanes, VD[i] = clamp(round_toward_zero(VB[i] * 2^UIMM), 0, UINT32_MAX). The 5-bit UIMM (bits 11..15) gives the Q-format fractional shift, in 0..31.
• Saturating, not wrapping. Negative inputs clamp to 0; values above 2^32 − 1 clamp to 0xFFFF_FFFF. NaN → 0. All clamping events sticky-set VSCR[SAT]. Xenia's crate::vmx::cvt_f32_to_u32_sat (crates/xenia-cpu/src/vmx.rs) handles the boundaries.
• VSCR[SAT] sticky. Cleared only by mtvscr.
• Rounding is truncate-toward-zero. Always.
• VSCR[NJ] flushes denormal inputs to zero before scaling (Xenon default).
• Big-endian word lanes. Lane 0 is the most-significant word.
• No XER changes, no traps.
• No VMX128 sibling.
• Common usage. Float colour [0.0, 1.0] → packed 0..2^N−1 integer with vctuxs vD, vColor, 8 (Q24.8 → 0..255 after a vpkshus) or , 32 for full unsigned-int range.

Related Instructions

• vctsxs — same shape, signed destination.
• vcfsx, vcfux — inverse direction.
• vrfin, vrfip, vrfim, vrfiz — float-to-float rounding modes.
• mtvscr / mfvscr — read or clear VSCR[SAT].

IBM Reference

• AIX 7.3 — vctuxs (Vector Convert to Unsigned Fixed-Point Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Conversion Instructions