xenia-rs/migration/project-root/ppc-manual/vmx/vupklsb.md

vupklsb — Vector Unpack Low Signed Byte

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000028e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vupklsb	vupklsb	—	Vector Unpack Low Signed Byte
vupklsb128	vupklsb128	—	Vector128 Unpack Low Signed Byte

Syntax

vupklsb [VD], [VB]
vupklsb128 [VD], [VB]

Encoding

vupklsb — form VX

• Opcode word: 0x1000028e
• Primary opcode (bits 0–5): 4
• Extended opcode: 654
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vupklsb128 — form VX128

• Opcode word: 0x180003c0
• Primary opcode (bits 0–5): 6
• Extended opcode: 960
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VB	vupklsb: read; vupklsb128: read	Source B vector register.
VD	vupklsb: write; vupklsb128: write	Destination vector register.

Register Effects

vupklsb

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vupklsb128

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vupklsb

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vupklsb"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:2076
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:129
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:494
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4144-4153

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vupklsb | PpcOpcode::vupklsb128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vupklsb128);
            let (rb, rd) = if is_128 { (instr.vb128(), instr.vd128()) }
                           else { (instr.rb(), instr.rd()) };
            let b = crate::vmx::as_i8x16(ctx.vr[rb]);
            let mut r = [0i16; 8];
            for i in 0..8 { r[i] = b[8 + i] as i16; }
            ctx.vr[rd] = crate::vmx::from_i16x8(r);
            ctx.pc += 4;
        }

vupklsb128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vupklsb128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:2079
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:129
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:701
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4144-4153

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vupklsb | PpcOpcode::vupklsb128 => {
            let is_128 = matches!(instr.opcode, PpcOpcode::vupklsb128);
            let (rb, rd) = if is_128 { (instr.vb128(), instr.vd128()) }
                           else { (instr.rb(), instr.rd()) };
            let b = crate::vmx::as_i8x16(ctx.vr[rb]);
            let mut r = [0i16; 8];
            for i in 0..8 { r[i] = b[8 + i] as i16; }
            ctx.vr[rd] = crate::vmx::from_i16x8(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Sign-extend the low 8 of 16 bytes into half-words. VB.b[8..15] are each reinterpreted as int8 and sign-extended to int16 in VD.h[0..7].
• Inverse of the low half of vpkshss / vpkshus (within the int8 range).
• Big-endian lane ordering.
• No saturation, no flags, no VSCR effect.
• VMX128 sibling vupklsb128.

Related Instructions

• vupkhsb — high-half byte unpack.
• vupkhsh, vupklsh — half-word → word unpacks.
• vpkshss, vpkshus — the inverse packs.
• vupkhpx, vupklpx — pixel-format unpacks.

IBM Reference

• AIX 7.3 — vupklsb (Vector Unpack Low Signed Byte)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting