xenia-rs

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MechaCat02 0f1130e2e6 [iterate-4C] JIT Phase 2a: native loads/stores + backed-memory diff tests

emit.rs: native x64 for the hot D/DS-form memory ops — lbz, lhz, lha, lwz,
stb, sth, stw, std. EA = (rA==0?0:gpr[rA]) + EXTS(disp) computed inline;
the access itself calls a focused extern "C" helper (jit_read_u*/
jit_store_u*) that reconstructs &dyn MemoryAccess (and &PpcContext for
stores) from JitEnv and calls the SAME big-endian trait methods the
interpreter uses -> MMIO routing / mem-watch / page-version bumps identical.
Stores replicate the interpreter arms' reservation-invalidation prologue
exactly (no-op without a reservation table). Load extension (zx8/zx16/
sx16/zx32) via movzx/movsx, matching each arm.

tests.rs: VecMem (backed big-endian mock) + loads_match/stores_match diff
tests (2000 seeds each) asserting GPR + full memory image + counters vs the
interpreter, incl. RA=0 and byte-swap.

Gate: golden n200m BYTE-IDENTICAL with XENIA_JIT=1; cargo test -p xenia-jit
green (9 tests). Throughput -n 200M --gpu-inline: 3.6s interp, 4.85s JIT
(down from 6.2s at Phase 1). Remaining fallback = branches (every block
terminator) + compares -> the crossover.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

2026-07-03 23:55:16 +02:00

xenia-analysis

[iterate-4A] Milestone-2: XMA audio decoder + RE tooling (dispatch recorder, analyzer vtable-fix, non-perturbing probes)

2026-06-21 21:38:19 +02:00

xenia-app

[iterate-4C] JIT Phase 0: dynasm skeleton (all-fallback, golden byte-identical)

2026-07-03 23:38:28 +02:00

xenia-apu

[iterate-4A] Milestone-2: XMA audio decoder + RE tooling (dispatch recorder, analyzer vtable-fix, non-perturbing probes)

2026-06-21 21:38:19 +02:00

xenia-cpu

[iterate-4C] JIT Phase 0: dynasm skeleton (all-fallback, golden byte-identical)