[iterate-4C] JIT Phase 2a: native loads/stores + backed-memory diff tests
emit.rs: native x64 for the hot D/DS-form memory ops — lbz, lhz, lha, lwz, stb, sth, stw, std. EA = (rA==0?0:gpr[rA]) + EXTS(disp) computed inline; the access itself calls a focused extern "C" helper (jit_read_u*/ jit_store_u*) that reconstructs &dyn MemoryAccess (and &PpcContext for stores) from JitEnv and calls the SAME big-endian trait methods the interpreter uses -> MMIO routing / mem-watch / page-version bumps identical. Stores replicate the interpreter arms' reservation-invalidation prologue exactly (no-op without a reservation table). Load extension (zx8/zx16/ sx16/zx32) via movzx/movsx, matching each arm. tests.rs: VecMem (backed big-endian mock) + loads_match/stores_match diff tests (2000 seeds each) asserting GPR + full memory image + counters vs the interpreter, incl. RA=0 and byte-swap. Gate: golden n200m BYTE-IDENTICAL with XENIA_JIT=1; cargo test -p xenia-jit green (9 tests). Throughput -n 200M --gpu-inline: 3.6s interp, 4.85s JIT (down from 6.2s at Phase 1). Remaining fallback = branches (every block terminator) + compares -> the crossover. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
MechaCat02
@@ -67,7 +67,12 @@ fn advance_and_count(ops: &mut Asm, off: &Offsets) {
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/// Try to emit native x64 for `instr`. Returns `true` if it fully handled the
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/// instruction (computation + `advance_and_count`); `false` if the caller must
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/// fall back to the interpreter for it.
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pub fn try_emit_native(ops: &mut Asm, off: &Offsets, instr: &DecodedInstr) -> bool {
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pub fn try_emit_native(
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ops: &mut Asm,
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off: &Offsets,
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helpers: &crate::MemHelpers,
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instr: &DecodedInstr,
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) -> bool {
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let ra = instr.ra();
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let rb = instr.rb();
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let rd = instr.rd(); // == rs()
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@@ -221,10 +226,108 @@ pub fn try_emit_native(ops: &mut Asm, off: &Offsets, instr: &DecodedInstr) -> bo
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advance_and_count(ops, off);
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true
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}
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// ===== Loads (D-form): rD = EXT(mem[(rA==0?0:gpr[rA]) + EXTS(D)]) =====
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PpcOpcode::lbz => {
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emit_load(ops, off, helpers.read_u8, ra, rd, instr.d(), Ext::Zx8);
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true
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}
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PpcOpcode::lhz => {
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emit_load(ops, off, helpers.read_u16, ra, rd, instr.d(), Ext::Zx16);
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true
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}
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PpcOpcode::lha => {
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emit_load(ops, off, helpers.read_u16, ra, rd, instr.d(), Ext::Sx16);
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true
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}
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PpcOpcode::lwz => {
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emit_load(ops, off, helpers.read_u32, ra, rd, instr.d(), Ext::Zx32);
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true
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}
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// ===== Stores: mem[(rA==0?0:gpr[rA]) + EXTS(D/DS)] = gpr[rS] =====
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PpcOpcode::stb => {
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emit_store(ops, off, helpers.store_u8, ra, rd, instr.d());
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true
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}
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PpcOpcode::sth => {
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emit_store(ops, off, helpers.store_u16, ra, rd, instr.d());
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true
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}
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PpcOpcode::stw => {
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emit_store(ops, off, helpers.store_u32, ra, rd, instr.d());
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true
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}
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PpcOpcode::std => {
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// DS-form displacement (14-bit signed << 2).
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emit_store(ops, off, helpers.store_u64, ra, rd, instr.ds());
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true
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}
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_ => false,
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}
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}
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/// Result-extension mode for a native load.
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#[derive(Clone, Copy)]
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enum Ext {
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Zx8,
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Zx16,
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Sx16,
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Zx32,
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}
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/// Compute the effective address `(rA==0 ? 0 : gpr[rA]) + EXTS(disp)` into
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/// `rsi` (the 2nd System-V arg). Only touches `rsi`. The helper takes a `u32`
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/// address, so the low 32 bits of `rsi` are the guest EA (matching the
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/// interpreter's `... as u32` truncation).
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#[inline]
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fn emit_ea(ops: &mut Asm, off: &Offsets, ra: usize, disp: i32) {
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if ra == 0 {
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dynasm!(ops ; .arch x64 ; xor esi, esi);
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} else {
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dynasm!(ops ; .arch x64 ; mov rsi, [r15 + off.gpr(ra)]);
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}
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if disp != 0 {
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dynasm!(ops ; .arch x64 ; add rsi, disp);
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}
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}
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/// Emit a native load: `rsi=ea; rdi=env; call read_helper; extend; gpr[rd]=res`.
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#[inline]
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fn emit_load(ops: &mut Asm, off: &Offsets, helper: i64, ra: usize, rd: usize, disp: i32, ext: Ext) {
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emit_ea(ops, off, ra, disp);
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dynasm!(ops
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; .arch x64
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; mov rdi, rbx
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; mov rax, QWORD helper
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; call rax
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);
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// Extend the return (in al/ax/eax) into rax, zeroing the upper bits per the
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// interpreter's `as ... as u64` extension chain.
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match ext {
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Ext::Zx8 => dynasm!(ops ; .arch x64 ; movzx eax, al),
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Ext::Zx16 => dynasm!(ops ; .arch x64 ; movzx eax, ax),
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Ext::Sx16 => dynasm!(ops ; .arch x64 ; movsx eax, ax),
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Ext::Zx32 => dynasm!(ops ; .arch x64 ; mov eax, eax),
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}
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dynasm!(ops ; .arch x64 ; mov [r15 + off.gpr(rd)], rax);
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advance_and_count(ops, off);
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}
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/// Emit a native store: `rsi=ea; rdx=gpr[rs]; rdi=env; call store_helper`.
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#[inline]
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fn emit_store(ops: &mut Asm, off: &Offsets, helper: i64, ra: usize, rs: usize, disp: i32) {
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emit_ea(ops, off, ra, disp);
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dynasm!(ops
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; .arch x64
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; mov rdx, [r15 + off.gpr(rs)]
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; mov rdi, rbx
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; mov rax, QWORD helper
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; call rax
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);
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advance_and_count(ops, off);
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}
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/// Load `gpr[ra]` into `rax`, or zero `rax` when `ra == 0` (the PPC
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/// arithmetic-D "RA=0 means literal 0" rule, statically known here).
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#[inline]
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@@ -96,6 +96,98 @@ unsafe extern "C" fn jit_interpret_one(env: *mut JitEnv, instr: *const DecodedIn
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sr_code(r)
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}
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// ---- memory-access helpers called from emitted load/store code ----
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//
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// Each reconstructs `&dyn MemoryAccess` (and, for stores, `&PpcContext`) from
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// the `JitEnv` and calls the SAME trait methods the interpreter uses, so MMIO
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// routing, mem-watch, and page-version bumps are byte-identical. Loads are pure
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// reads; stores replicate the interpreter store arms' reservation-invalidation
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// prologue exactly (a no-op when no reservation table is installed).
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/// SAFETY (all helpers): `env` is the live `JitEnv` from [`run_jit_block`];
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/// `env.ctx`/`env.mem` are valid for the block call. Big-endian handling lives
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/// in the trait methods, matching the interpreter.
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unsafe extern "C" fn jit_read_u8(env: *mut JitEnv, addr: u32) -> u8 {
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let mem: &dyn MemoryAccess = unsafe { &*(&*env).mem };
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mem.read_u8(addr)
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}
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unsafe extern "C" fn jit_read_u16(env: *mut JitEnv, addr: u32) -> u16 {
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let mem: &dyn MemoryAccess = unsafe { &*(&*env).mem };
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mem.read_u16(addr)
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}
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unsafe extern "C" fn jit_read_u32(env: *mut JitEnv, addr: u32) -> u32 {
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let mem: &dyn MemoryAccess = unsafe { &*(&*env).mem };
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mem.read_u32(addr)
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}
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unsafe extern "C" fn jit_read_u64(env: *mut JitEnv, addr: u32) -> u64 {
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let mem: &dyn MemoryAccess = unsafe { &*(&*env).mem };
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mem.read_u64(addr)
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}
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/// Reservation invalidation shared by all store arms (mirrors
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/// `interpreter.rs`: invalidate a same-line reservation before a write; no-op
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/// unless a reservation table is installed and enabled with active reservers).
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#[inline]
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unsafe fn store_reservation_invalidate(env: &JitEnv, ea: u32) {
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let ctx = unsafe { &*env.ctx };
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if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
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if t.has_active_reservers() {
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t.invalidate_for_write(ea);
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}
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}
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}
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unsafe extern "C" fn jit_store_u8(env: *mut JitEnv, addr: u32, val: u64) {
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let env = unsafe { &*env };
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unsafe { store_reservation_invalidate(env, addr) };
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let mem: &dyn MemoryAccess = unsafe { &*env.mem };
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mem.write_u8(addr, val as u8);
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}
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unsafe extern "C" fn jit_store_u16(env: *mut JitEnv, addr: u32, val: u64) {
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let env = unsafe { &*env };
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unsafe { store_reservation_invalidate(env, addr) };
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let mem: &dyn MemoryAccess = unsafe { &*env.mem };
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mem.write_u16(addr, val as u16);
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}
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unsafe extern "C" fn jit_store_u32(env: *mut JitEnv, addr: u32, val: u64) {
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let env = unsafe { &*env };
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unsafe { store_reservation_invalidate(env, addr) };
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let mem: &dyn MemoryAccess = unsafe { &*env.mem };
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mem.write_u32(addr, val as u32);
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}
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unsafe extern "C" fn jit_store_u64(env: *mut JitEnv, addr: u32, val: u64) {
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let env = unsafe { &*env };
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unsafe { store_reservation_invalidate(env, addr) };
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let mem: &dyn MemoryAccess = unsafe { &*env.mem };
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mem.write_u64(addr, val);
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}
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/// Absolute addresses of the memory helpers, baked into emitted code.
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pub(crate) struct MemHelpers {
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pub read_u8: i64,
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pub read_u16: i64,
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pub read_u32: i64,
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pub read_u64: i64,
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pub store_u8: i64,
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pub store_u16: i64,
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pub store_u32: i64,
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pub store_u64: i64,
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}
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impl MemHelpers {
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pub(crate) fn resolve() -> Self {
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MemHelpers {
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read_u8: jit_read_u8 as usize as i64,
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read_u16: jit_read_u16 as usize as i64,
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read_u32: jit_read_u32 as usize as i64,
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read_u64: jit_read_u64 as usize as i64,
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store_u8: jit_store_u8 as usize as i64,
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store_u16: jit_store_u16 as usize as i64,
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store_u32: jit_store_u32 as usize as i64,
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store_u64: jit_store_u64 as usize as i64,
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}
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}
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}
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/// One JIT-compiled block. Owns everything the emitted code references so the
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/// code, its instruction pointers, and its cache-key metadata share one
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/// lifetime.
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@@ -127,8 +219,9 @@ fn compile_block(block: &DecodedBlock) -> CompiledBlock {
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// copy (its addresses are final once boxed).
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let instrs: Box<[DecodedInstr]> = block.instrs.clone().into_boxed_slice();
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// Field offsets resolved at compile time — robust to struct layout.
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// Field offsets + helper addresses resolved at compile time.
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let off = emit::Offsets::resolve();
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let mem_helpers = MemHelpers::resolve();
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let helper = jit_interpret_one as usize as i64;
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let mut ops = dynasmrt::x64::Assembler::new().expect("dynasm assembler");
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@@ -152,7 +245,7 @@ fn compile_block(block: &DecodedBlock) -> CompiledBlock {
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// Native fast path: emitters fully handle the instruction (compute +
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// pc+=4 + counter bumps) and never diverge control flow, so no exit
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// checks are needed after them.
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if emit::try_emit_native(&mut ops, &off, instr) {
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if emit::try_emit_native(&mut ops, &off, &mem_helpers, instr) {
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continue;
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}
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// Interpreter fallback for un-ported opcodes.
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@@ -50,6 +50,90 @@ impl MemoryAccess for NoMem {
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}
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}
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/// Backed big-endian memory for load/store differential tests. Byte-wise access
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/// with per-byte wrap masking so both the interpreter and the JIT hit the same
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/// bytes for any EA — a divergence means the JIT computed a different EA or
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/// mishandled the value.
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struct VecMem {
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data: std::cell::RefCell<Vec<u8>>,
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}
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impl VecMem {
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const LEN: usize = 1 << 16;
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fn seeded() -> Self {
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// Deterministic non-trivial pattern so loads read distinguishable bytes.
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let mut v = vec![0u8; Self::LEN];
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for (i, b) in v.iter_mut().enumerate() {
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*b = (i as u8) ^ 0xA5;
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}
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VecMem {
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data: std::cell::RefCell::new(v),
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}
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}
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fn snapshot(&self) -> Vec<u8> {
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self.data.borrow().clone()
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}
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#[inline]
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fn idx(a: u32, i: u32) -> usize {
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(a.wrapping_add(i) as usize) & (Self::LEN - 1)
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}
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}
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impl MemoryAccess for VecMem {
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fn read_u8(&self, a: u32) -> u8 {
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self.data.borrow()[Self::idx(a, 0)]
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}
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fn read_u16(&self, a: u32) -> u16 {
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let d = self.data.borrow();
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u16::from_be_bytes([d[Self::idx(a, 0)], d[Self::idx(a, 1)]])
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}
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fn read_u32(&self, a: u32) -> u32 {
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let d = self.data.borrow();
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u32::from_be_bytes([
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d[Self::idx(a, 0)],
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d[Self::idx(a, 1)],
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d[Self::idx(a, 2)],
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d[Self::idx(a, 3)],
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])
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}
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fn read_u64(&self, a: u32) -> u64 {
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let d = self.data.borrow();
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let mut b = [0u8; 8];
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for (i, bb) in b.iter_mut().enumerate() {
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*bb = d[Self::idx(a, i as u32)];
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}
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u64::from_be_bytes(b)
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}
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fn write_u8(&self, a: u32, v: u8) {
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self.data.borrow_mut()[Self::idx(a, 0)] = v;
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}
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fn write_u16(&self, a: u32, v: u16) {
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let b = v.to_be_bytes();
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let mut d = self.data.borrow_mut();
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for (i, bb) in b.iter().enumerate() {
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d[Self::idx(a, i as u32)] = *bb;
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}
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}
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fn write_u32(&self, a: u32, v: u32) {
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let b = v.to_be_bytes();
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let mut d = self.data.borrow_mut();
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for (i, bb) in b.iter().enumerate() {
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d[Self::idx(a, i as u32)] = *bb;
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}
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}
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fn write_u64(&self, a: u32, v: u64) {
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let b = v.to_be_bytes();
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let mut d = self.data.borrow_mut();
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for (i, bb) in b.iter().enumerate() {
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d[Self::idx(a, i as u32)] = *bb;
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}
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}
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fn translate(&self, _: u32) -> Option<*const u8> {
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None
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}
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fn translate_mut(&self, _: u32) -> Option<*mut u8> {
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None
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}
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}
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// ---- instruction encoders (PPC big-endian field layout; `raw` is the u32) ----
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/// D-form: `op | b6_10<<21 | b11_15<<16 | imm16`.
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@@ -90,9 +174,10 @@ fn check(raw: u32, gpr: [u64; 32]) {
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// Guard: the opcode must actually be natively emitted (else this test is
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// vacuous — a fallback would trivially match).
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let helpers = crate::MemHelpers::resolve();
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let mut probe = dynasmrt::x64::Assembler::new().unwrap();
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assert!(
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emit::try_emit_native(&mut probe, &off, &instr),
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emit::try_emit_native(&mut probe, &off, &helpers, &instr),
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"opcode not natively emitted for raw={raw:#010x} ({:?})",
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instr.opcode
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);
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@@ -205,6 +290,7 @@ fn arith_reg_matches() {
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#[test]
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fn recording_and_hint_forms_fall_back() {
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let off = emit::Offsets::resolve();
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let helpers = crate::MemHelpers::resolve();
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let mut probe = dynasmrt::x64::Assembler::new().unwrap();
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let cases = [
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enc_xo(31, 3, 4, 5, 0, 266, 1), // add.
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@@ -215,9 +301,97 @@ fn recording_and_hint_forms_fall_back() {
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for raw in cases {
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let instr = decode(raw, 0x8200_1000);
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assert!(
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!emit::try_emit_native(&mut probe, &off, &instr),
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!emit::try_emit_native(&mut probe, &off, &helpers, &instr),
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"raw={raw:#010x} ({:?}) should fall back, not native",
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instr.opcode
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);
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}
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}
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/// Load/store differential test with backed memory: verify GPR + memory +
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/// counters match the interpreter for random bases/displacements, incl. the
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/// RA=0 form and the byte-swap / sign-vs-zero extension.
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fn check_mem(raw: u32, gpr: [u64; 32]) {
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let pc = 0x8200_1000u32;
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let instr = decode(raw, pc);
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let off = emit::Offsets::resolve();
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let helpers = crate::MemHelpers::resolve();
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let mut probe = dynasmrt::x64::Assembler::new().unwrap();
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assert!(
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emit::try_emit_native(&mut probe, &off, &helpers, &instr),
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"mem opcode not natively emitted raw={raw:#010x} ({:?})",
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instr.opcode
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);
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let mem_a = VecMem::seeded();
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let mut a = ctx_from_gpr(gpr, pc);
|
||||
let ra = interpret_one(&mut a, &mem_a, &instr);
|
||||
a.cycle_count += 1;
|
||||
a.timebase += 1;
|
||||
|
||||
let mem_b = VecMem::seeded();
|
||||
let mut b = ctx_from_gpr(gpr, pc);
|
||||
let block = DecodedBlock {
|
||||
start_pc: pc,
|
||||
end_pc: pc.wrapping_add(4),
|
||||
page_version: 0,
|
||||
instrs: vec![instr],
|
||||
sync_sensitive: false,
|
||||
};
|
||||
let cb: CompiledBlock = compile_block(&block);
|
||||
let rb = run_jit_block(&cb, &mut b, &mem_b);
|
||||
|
||||
assert_eq!(a.gpr, b.gpr, "gpr mismatch raw={raw:#010x} ({:?})", instr.opcode);
|
||||
assert_eq!(a.pc, b.pc, "pc mismatch raw={raw:#010x}");
|
||||
assert_eq!(a.cycle_count, b.cycle_count, "cycle mismatch raw={raw:#010x}");
|
||||
assert_eq!(a.timebase, b.timebase, "timebase mismatch raw={raw:#010x}");
|
||||
assert_eq!(
|
||||
mem_a.snapshot(),
|
||||
mem_b.snapshot(),
|
||||
"memory mismatch raw={raw:#010x} ({:?})",
|
||||
instr.opcode
|
||||
);
|
||||
assert_eq!(ra, rb, "StepResult mismatch raw={raw:#010x}");
|
||||
}
|
||||
|
||||
/// Random gpr seed with a controlled base register so EAs land in the mock.
|
||||
fn fuzz_gpr_based(seed: &mut u64, ra: u32) -> [u64; 32] {
|
||||
let mut g = fuzz_gpr(seed);
|
||||
if ra != 0 {
|
||||
// Base within the 64 KiB mock, away from the wrap edge.
|
||||
g[ra as usize] = 0x2000 + (rng(seed) & 0x1FFF);
|
||||
}
|
||||
g
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn loads_match() {
|
||||
let mut s = 0x11ffu64;
|
||||
for _ in 0..ITERS {
|
||||
let rd = (rng(&mut s) % 32) as u32;
|
||||
let ra = (rng(&mut s) % 32) as u32;
|
||||
let disp = (rng(&mut s) & 0x7F) as u16; // small non-negative displacement
|
||||
let g = fuzz_gpr_based(&mut s, ra);
|
||||
check_mem(enc_d(34, rd, ra, disp), g); // lbz
|
||||
check_mem(enc_d(40, rd, ra, disp), g); // lhz
|
||||
check_mem(enc_d(42, rd, ra, disp), g); // lha
|
||||
check_mem(enc_d(32, rd, ra, disp), g); // lwz
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn stores_match() {
|
||||
let mut s = 0x22eeu64;
|
||||
for _ in 0..ITERS {
|
||||
let rs = (rng(&mut s) % 32) as u32;
|
||||
let ra = (rng(&mut s) % 32) as u32;
|
||||
let disp = (rng(&mut s) & 0x7F) as u16;
|
||||
let g = fuzz_gpr_based(&mut s, ra);
|
||||
check_mem(enc_d(38, rs, ra, disp), g); // stb
|
||||
check_mem(enc_d(44, rs, ra, disp), g); // sth
|
||||
check_mem(enc_d(36, rs, ra, disp), g); // stw
|
||||
// std: DS-form, opcode 62, low 2 bits (XO) = 0; disp must be a
|
||||
// multiple of 4 (bits 0-1 are the XO field).
|
||||
check_mem((62 << 26) | (rs << 21) | (ra << 16) | ((disp as u32 & 0x3FFC)), g);
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user