78ea81c12a
Per canary AluInstruction layout (xenia-canary/src/xenia/gpu/ucode.h:
2078-2086), word-0 bits 29-31 are the per-operand `srcN_sel` flags
selecting temp register (1) vs ALU constant (0); the corresponding
8-bit src byte indexes either:
- a temp register (bits 5:0 = index, bits 6/7 reserved for
relative-addressing / abs flags consumed by Phase D2), or
- an ALU constant (full 8-bit index).
Pre-fix, the WGSL interpreter and AOT translator both masked `& 0x7F`
on the src byte and emitted `r[low7]` regardless of the operand class.
Every shader's WVP matrix / light constant / per-frame uniform read
came back as r[low7] — typically zero — yielding invisible rendering.
Mechanical changes:
- crates/xenia-gpu/src/ucode/alu.rs: decode src_a_is_temp /
src_b_is_temp / src_c_is_temp from w0 bits 29/30/31. Note that our
src_a (low byte of w0) is canary's third operand, hence its selector
is bit 29 (canary src3_sel), not bit 31.
- crates/xenia-gpu/src/shaders/xenos_interp.wgsl: `read_src` now takes
the is_temp flag; constants index xenos_consts.alu directly.
- crates/xenia-gpu/src/translator.rs: `src_operand` mirrors the
interpreter — `r[idx]` when temp, `xenos_consts.alu[idx]` when
constant.
The trivial-shader synthetic test was updated to set the temp flags so
its `r[0u] = (r[0u] + r[0u])` assertion remains valid; without the
flags set, all sources would now resolve as constants.
Bank-selection (cf-level relative addressing for higher banks of the
512 ALU constants) remains a Phase G+ extension — covers c0..c127
in bank 0, which most Sylpheed shaders use directly.
Verification at -n 100M lockstep:
swaps: 2 → 2 (unchanged — gated by D2/D3/E for draws)
draws: 0 → 0
packets: ~61M (within noise)
Tests: 552 → 554 (+2 translator tests for the temp/constant decode).
Closes GPUBUG-101 (P0).
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
226 lines
8.0 KiB
Rust
226 lines
8.0 KiB
Rust
//! Xenos ALU (vector + scalar) instruction decoder.
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//!
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//! An ALU instruction is 96 bits = 3 dwords. The three dwords encode:
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//! - word0: operand modifier flags + destination info
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//! - word1: source register / swizzle fields
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//! - word2: opcode + write mask + export target
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//!
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//! See `ucode.h:900-1400` for the full field map. This decoder captures the
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//! minimal shape the uber-shader needs; flags we don't interpret yet are
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//! retained as raw bits in `raw` for downstream inspection.
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/// Decoded ALU instruction.
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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pub struct AluInstruction {
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/// Vector ALU opcode (bits 0..6 of word2 in canary's layout).
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pub vector_opcode: u8,
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/// Scalar ALU opcode (bits 7..13 of word2).
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pub scalar_opcode: u8,
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/// Destination register index for vector result (7 bits).
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pub vector_dest: u8,
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/// Destination register index for scalar result (7 bits).
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pub scalar_dest: u8,
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/// 4-bit write mask for the vector result (x/y/z/w).
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pub vector_write_mask: u8,
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/// 4-bit write mask for the scalar result.
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pub scalar_write_mask: u8,
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/// Set when the instruction should write to the export bank (position,
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/// interpolators, color, etc.) instead of the general register file.
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pub vector_dest_is_export: bool,
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/// Selects `ps` (previous scalar result) as the scalar operand when set.
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pub scalar_src_is_ps: bool,
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/// Source register indices (at most 3 for vector ops). The src bytes
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/// are the canary `srcN_reg` fields (8 bits each); for **temp-typed**
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/// operands (see `src_a_is_temp` etc.), bit 7 of the byte is the abs
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/// flag and bit 6 is the loop-relative flag — bits 5:0 give the temp
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/// index. For **constant-typed** operands the full byte is the
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/// constant index.
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pub src_a: u8,
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pub src_b: u8,
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pub src_c: u8,
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/// Per-operand "is temporary" flag — when true, the corresponding
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/// `src_X` byte indexes a general register (r#); when false, it
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/// indexes an ALU constant (c#). Decoded from word-0 bits 29-31
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/// (canary's `src3_sel`/`src2_sel`/`src1_sel`). GPUBUG-101.
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pub src_a_is_temp: bool,
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pub src_b_is_temp: bool,
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pub src_c_is_temp: bool,
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/// Set when the instruction is predicated; skipped if the predicate
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/// doesn't match `predicate_condition`.
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pub predicated: bool,
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pub predicate_condition: bool,
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/// Raw dwords — preserved verbatim so the translator / interpreter can
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/// reach into fields we haven't parsed explicitly yet.
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pub raw: [u32; 3],
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}
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/// Decode a 3-dword ALU triple.
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pub fn decode_alu(words: [u32; 3]) -> AluInstruction {
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let w0 = words[0];
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let _w1 = words[1];
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let w2 = words[2];
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AluInstruction {
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vector_opcode: (w2 & 0x3F) as u8,
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scalar_opcode: ((w2 >> 6) & 0x3F) as u8,
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vector_dest: ((w2 >> 16) & 0x7F) as u8,
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scalar_dest: ((w2 >> 24) & 0x7F) as u8,
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vector_write_mask: ((w2 >> 12) & 0xF) as u8,
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scalar_write_mask: ((w2 >> 8) & 0xF) as u8,
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vector_dest_is_export: ((w2 >> 23) & 1) != 0,
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scalar_src_is_ps: ((w0 >> 26) & 1) != 0,
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src_a: (w0 & 0xFF) as u8,
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src_b: ((w0 >> 8) & 0xFF) as u8,
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src_c: ((w0 >> 16) & 0xFF) as u8,
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// Word-0 bits 29-31 are the per-operand temp-vs-constant
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// selector (canary `src3_sel`/`src2_sel`/`src1_sel`,
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// ucode.h:2078-2086). Our `src_a` is canary's third operand
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// (low byte of w0), so its selector is bit 29.
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src_a_is_temp: ((w0 >> 29) & 1) != 0,
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src_b_is_temp: ((w0 >> 30) & 1) != 0,
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src_c_is_temp: ((w0 >> 31) & 1) != 0,
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predicated: ((w0 >> 27) & 1) != 0,
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predicate_condition: ((w0 >> 28) & 1) != 0,
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raw: words,
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}
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}
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/// Vector ALU opcodes we reference by name. Values match canary's
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/// `AluVectorOpcode` enum in `ucode.h:1354`.
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pub mod vop {
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pub const ADD: u8 = 0;
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pub const MUL: u8 = 1;
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pub const MAX: u8 = 2;
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pub const MIN: u8 = 3;
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pub const SEQ: u8 = 4;
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pub const SGT: u8 = 5;
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pub const SGE: u8 = 6;
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pub const SNE: u8 = 7;
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pub const FRC: u8 = 8;
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pub const TRUNC: u8 = 9;
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pub const FLOOR: u8 = 10;
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pub const MAD: u8 = 11;
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pub const CND_EQ: u8 = 12;
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pub const CND_GE: u8 = 13;
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pub const CND_GT: u8 = 14;
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pub const DOT4: u8 = 15;
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pub const DOT3: u8 = 16;
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pub const DOT2_ADD: u8 = 17;
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pub const CUBE: u8 = 18;
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pub const MAX4: u8 = 19;
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pub const SETP_EQ_PUSH: u8 = 20;
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pub const SETP_NE_PUSH: u8 = 21;
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pub const SETP_GT_PUSH: u8 = 22;
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pub const SETP_GE_PUSH: u8 = 23;
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pub const KILL_EQ: u8 = 24;
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pub const KILL_GT: u8 = 25;
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pub const KILL_GE: u8 = 26;
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pub const KILL_NE: u8 = 27;
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pub const DST: u8 = 28;
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pub const MAX_A: u8 = 29;
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}
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/// Scalar ALU opcodes. Values match canary's `AluScalarOpcode` enum in
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/// `ucode.h:1001`.
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pub mod sop {
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pub const ADDS: u8 = 0;
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pub const ADDS_PREV: u8 = 1;
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pub const MULS: u8 = 2;
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pub const MULS_PREV: u8 = 3;
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pub const MULS_PREV2: u8 = 4;
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pub const MAXS: u8 = 5;
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pub const MINS: u8 = 6;
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pub const SEQS: u8 = 7;
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pub const SGTS: u8 = 8;
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pub const SGES: u8 = 9;
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pub const SNES: u8 = 10;
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pub const FRCS: u8 = 11;
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pub const TRUNCS: u8 = 12;
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pub const FLOORS: u8 = 13;
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pub const EXP: u8 = 14;
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pub const LOGC: u8 = 15;
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pub const LOG: u8 = 16;
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pub const RCPC: u8 = 17;
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pub const RCPF: u8 = 18;
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pub const RCP: u8 = 19;
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pub const RSQC: u8 = 20;
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pub const RSQF: u8 = 21;
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pub const RSQ: u8 = 22;
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pub const MAXAS: u8 = 23;
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pub const MAXASF: u8 = 24;
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pub const SUBS: u8 = 25;
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pub const SUBS_PREV: u8 = 26;
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pub const SETP_EQ: u8 = 27;
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pub const SETP_NE: u8 = 28;
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pub const SETP_GT: u8 = 29;
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pub const SETP_GE: u8 = 30;
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pub const SETP_INV: u8 = 31;
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pub const SETP_POP: u8 = 32;
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pub const SETP_CLR: u8 = 33;
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pub const SETP_RSTR: u8 = 34;
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pub const KILLS_EQ: u8 = 35;
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pub const KILLS_GT: u8 = 36;
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pub const KILLS_GE: u8 = 37;
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pub const KILLS_NE: u8 = 38;
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pub const KILLS_ONE: u8 = 39;
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pub const SQRT: u8 = 40;
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pub const MULSC0: u8 = 42;
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pub const MULSC1: u8 = 43;
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pub const ADDSC0: u8 = 44;
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pub const ADDSC1: u8 = 45;
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pub const SUBSC0: u8 = 46;
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pub const SUBSC1: u8 = 47;
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pub const SIN: u8 = 48;
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pub const COS: u8 = 49;
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pub const RETAIN_PREV: u8 = 50;
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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/// Regression: our table previously drifted from canary's values (e.g.
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/// `MAXS=6` when canary says 5, shifting everything through SQRT). Pin
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/// the most-often-used scalar + vector opcodes here.
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#[test]
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fn opcodes_match_canary_values() {
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// Scalar.
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assert_eq!(sop::MAXS, 5);
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assert_eq!(sop::MINS, 6);
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assert_eq!(sop::SEQS, 7);
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assert_eq!(sop::EXP, 14);
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assert_eq!(sop::LOG, 16);
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assert_eq!(sop::RCP, 19);
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assert_eq!(sop::RSQ, 22);
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assert_eq!(sop::SUBS, 25);
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assert_eq!(sop::SETP_EQ, 27);
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assert_eq!(sop::KILLS_EQ, 35);
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assert_eq!(sop::SQRT, 40);
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assert_eq!(sop::SIN, 48);
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assert_eq!(sop::RETAIN_PREV, 50);
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// Vector.
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assert_eq!(vop::SNE, 7);
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assert_eq!(vop::CND_EQ, 12);
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assert_eq!(vop::MAX4, 19);
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assert_eq!(vop::KILL_EQ, 24);
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assert_eq!(vop::DST, 28);
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}
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#[test]
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fn decode_extracts_opcodes_and_dests() {
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// Build a minimal ALU word:
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// vector_opcode = ADD (0), scalar_opcode = RCP (22),
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// vector_dest = 3, scalar_dest = 7, vector_write_mask = 0xF
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let w2 = (vop::ADD as u32)
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| ((sop::RCP as u32) << 6)
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| (0xF << 12) // vector_write_mask
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| (3u32 << 16) // vector_dest
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| (7u32 << 24); // scalar_dest
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let alu = decode_alu([0, 0, w2]);
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assert_eq!(alu.vector_opcode, vop::ADD);
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assert_eq!(alu.scalar_opcode, sop::RCP);
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assert_eq!(alu.vector_dest, 3);
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assert_eq!(alu.scalar_dest, 7);
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assert_eq!(alu.vector_write_mask, 0xF);
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}
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}
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