ef93a4fa14
Source changes (dormant parity infra, retained from iterate 2.AI/2.AO): - xenia-kernel/exports.rs: nt_create_event manual_reset polarity + related event wiring - xenia-gpu/mmio_region.rs: D1MODE_VBLANK_VLINE_STATUS hardcode parity Also lands the audit-runs/ analysis notes (.md/.txt/.json digests) for the iterate 2.x VSync/0x10e8/0x1004 wedge investigation. Raw trace dumps (.jsonl/.gz/.csv/.stdout) and agent worktrees (.claude/) are gitignored as regenerable local artifacts — see memory + HANDOFF for the running findings. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
77 lines
2.8 KiB
Diff
77 lines
2.8 KiB
Diff
diff --git a/src/xenia/cpu/backend/x64/x64_emitter.cc b/src/xenia/cpu/backend/x64/x64_emitter.cc
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index 5da8f6adc..87d686c5c 100644
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--- a/src/xenia/cpu/backend/x64/x64_emitter.cc
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+++ b/src/xenia/cpu/backend/x64/x64_emitter.cc
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@@ -438,6 +438,19 @@ uint64_t TrapDebugBreak(void* raw_context, uint64_t address) {
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return 0;
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}
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+// AUDIT-030 / AUDIT-059: log LR + r3..r6 when `log_lr_on_pc` PC is reached.
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+uint64_t TrapLogLR(void* raw_context, uint64_t address) {
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+ auto* ctx = reinterpret_cast<ppc::PPCContext_s*>(raw_context);
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+ XELOGI(
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+ "TRACE-PC-LR pc={:08X} lr={:08X} r3={:08X} r4={:08X} r5={:08X} "
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+ "r6={:08X} r31={:08X}",
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+ static_cast<uint32_t>(cvars::log_lr_on_pc),
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+ static_cast<uint32_t>(ctx->lr), static_cast<uint32_t>(ctx->r[3]),
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+ static_cast<uint32_t>(ctx->r[4]), static_cast<uint32_t>(ctx->r[5]),
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+ static_cast<uint32_t>(ctx->r[6]), static_cast<uint32_t>(ctx->r[31]));
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+ return 0;
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+}
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+
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void X64Emitter::Trap(uint16_t trap_type) {
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switch (trap_type) {
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case 20:
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@@ -454,6 +467,10 @@ void X64Emitter::Trap(uint16_t trap_type) {
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case 25:
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// ?
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break;
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+ case 100:
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+ // AUDIT-030 / AUDIT-059: log LR + r3..r6 (set via --log_lr_on_pc).
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+ CallNative(TrapLogLR, 0);
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+ break;
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default:
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XELOGW("Unknown trap type {}", trap_type);
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db(0xCC);
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diff --git a/src/xenia/cpu/cpu_flags.cc b/src/xenia/cpu/cpu_flags.cc
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index 3ff067e15..fa2601336 100644
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--- a/src/xenia/cpu/cpu_flags.cc
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+++ b/src/xenia/cpu/cpu_flags.cc
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@@ -57,3 +57,8 @@ DEFINE_bool(break_condition_truncate, true, "truncate value to 32-bits", "CPU");
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DEFINE_bool(break_on_debugbreak, true, "int3 on JITed __debugbreak requests.",
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"CPU");
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+
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+// AUDIT-030 / AUDIT-059: log LR + r3..r6 each time the given guest PC executes.
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+DEFINE_uint64(log_lr_on_pc, 0,
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+ "Log LR + r3..r6 each time the given guest PC is executed.",
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+ "CPU");
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diff --git a/src/xenia/cpu/cpu_flags.h b/src/xenia/cpu/cpu_flags.h
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index 38c4f98ba..ad3d78581 100644
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--- a/src/xenia/cpu/cpu_flags.h
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+++ b/src/xenia/cpu/cpu_flags.h
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@@ -35,4 +35,6 @@ DECLARE_bool(break_condition_truncate);
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DECLARE_bool(break_on_debugbreak);
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+DECLARE_uint64(log_lr_on_pc);
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+
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#endif // XENIA_CPU_CPU_FLAGS_H_
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diff --git a/src/xenia/cpu/ppc/ppc_hir_builder.cc b/src/xenia/cpu/ppc/ppc_hir_builder.cc
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index 42d996cba..679b09bb1 100644
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--- a/src/xenia/cpu/ppc/ppc_hir_builder.cc
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+++ b/src/xenia/cpu/ppc/ppc_hir_builder.cc
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@@ -174,6 +174,12 @@ bool PPCHIRBuilder::Emit(GuestFunction* function, uint32_t flags) {
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MaybeBreakOnInstruction(address);
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+ // AUDIT-030 / AUDIT-059: log LR + r3..r6 each time `log_lr_on_pc` reached.
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+ if (cvars::log_lr_on_pc != 0 && address == cvars::log_lr_on_pc) {
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+ Comment("--log-lr-on-pc target");
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+ Trap(100);
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+ }
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+
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InstrData i;
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i.address = address;
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i.code = code;
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