ef93a4fa14
Source changes (dormant parity infra, retained from iterate 2.AI/2.AO): - xenia-kernel/exports.rs: nt_create_event manual_reset polarity + related event wiring - xenia-gpu/mmio_region.rs: D1MODE_VBLANK_VLINE_STATUS hardcode parity Also lands the audit-runs/ analysis notes (.md/.txt/.json digests) for the iterate 2.x VSync/0x10e8/0x1004 wedge investigation. Raw trace dumps (.jsonl/.gz/.csv/.stdout) and agent worktrees (.claude/) are gitignored as regenerable local artifacts — see memory + HANDOFF for the running findings. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
50 lines
2.7 KiB
Diff
50 lines
2.7 KiB
Diff
--- a/xenia-rs/tools/diff-events/diff_events.py
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+++ b/xenia-rs/tools/diff-events/diff_events.py
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@@ -287,6 +287,25 @@ ALLOCATOR_RETURN_FNS = frozenset(
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# creation call.
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"XamNotifyCreateListener",
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+ # Phase C+25: `MmGetPhysicalAddress` is a VA→PA translator whose
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+ # return depends on which heap region the input VA lives in. This
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+ # is the downstream consequence of C+2's deferred Path β (canary
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+ # has three physical heaps at vA0/vC0/vE0 routed by page size,
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+ # ours has a single unified heap_cursor starting at 0x40000000).
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+ # Concretely: at C+25 idx 105,112 canary returned 0x150B0000
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+ # (input 0xF50AF000 in `vE0000000` heap: addr - 0xE0000000 + 0x1000
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+ # per `PhysicalHeap::GetPhysicalAddress`, see `memory.cc:2317`),
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+ # while ours returned 0x0ADCF000 (input ~0x4ADCF000 in unified heap,
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+ # masked via `& 0x1FFF_FFFF` per `exports.rs:985`). Both engines'
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+ # translations are SELF-CONSISTENT — game code passes the PA
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+ # opaquely to GPU (`VdInitializeRingBuffer` is the very next call)
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+ # and the GPU translates it back to a host pointer using the same
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+ # engine's heap map. Per-(tid,name) ordinal sentinel preserves the
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+ # opaque-pass-through semantics while exposing actual divergences
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+ # (e.g. game-side arithmetic on the PA, or a translation-count
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+ # mismatch). Lifting the engine-side three-physical-heaps memory
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+ # model is the C+2 Path β deferral, out of scope for C+25 (see
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+ # `project_phase_c2_MmAllocatePhysicalMemoryEx_2026_05_13.md`).
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+ "MmGetPhysicalAddress",
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]
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)
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--- a/xenia-rs/tools/diff-events/test_diff_events.py
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+++ b/xenia-rs/tools/diff-events/test_diff_events.py
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@@ -686,6 +686,150 @@ def test_collect_shared_global_sids_single_tid_excluded() -> None:
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+# === Phase C+25 — MmGetPhysicalAddress canonicalization ===
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+# (4 new tests; see investigation.md for details)
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+def test_mm_get_physical_address_in_allocator_set() -> None: ...
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+def test_mm_get_physical_address_canonicalization() -> None: ...
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+def test_mm_get_physical_address_cross_engine_alignment() -> None: ...
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+def test_mm_get_physical_address_count_mismatch_still_diverges() -> None: ...
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+
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def main() -> int:
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...
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# Phase C+25
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test_mm_get_physical_address_in_allocator_set()
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test_mm_get_physical_address_canonicalization()
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test_mm_get_physical_address_cross_engine_alignment()
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test_mm_get_physical_address_count_mismatch_still_diverges()
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Engine: UNTOUCHED. Python-only fix. Phase B image_canonical_sha256 ea8d160e…
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UNCHANGED by definition (no Rust source modified). Build clean. Kernel tests
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217 pass unchanged.
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