xenia-rs/migration/project-root/ppc-manual/alu/addis.md

# `addis` — Add Immediate Shifted

> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0x3c000000`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `addis` | `addis` | — | Add Immediate Shifted |

## Syntax

```asm
addis [RD], [RA0], [SIMM]
```

## Encoding

### `addis` — form `D`

- **Opcode word:** `0x3c000000`
- **Primary opcode (bits 0–5):** `15`
- **Extended opcode:** —
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS when storing) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `RA0` | addis: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `SIMM` | addis: read | 16-bit signed immediate. Sign-extended to 64 bits before use. |
| `RD` | addis: write | Destination GPR. |

## Register Effects

### `addis`

- **Reads (always):** `RA0`, `SIMM`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
if RA = 0 then RT <- EXTS(SIMM) << 16
else             RT <- (RA) + (EXTS(SIMM) << 16)
```

## C Translation Example

```c
/* addis RT, RA, SIMM  — RA=0 means literal 0                     */
uint64_t base = (insn.RA == 0) ? 0 : r[insn.RA];
r[insn.RT] = base + ((uint64_t)(int64_t)(int16_t)insn.SIMM << 16);
```

## Implementation References

**`addis`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="addis"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:138`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_alu.cc#L138)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:8`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L8)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:339`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L339)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:121-134`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L121-L134)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::addis => {
            // Xbox 360 user mode is 32-bit ABI (MSR.SF=0), so addis must
            // produce a value whose upper 32 bits don't pollute downstream
            // 64-bit arithmetic. The PPC ISA in 64-bit mode sign-extends
            // simm16 before the shift, producing 0xFFFFFFFF_xxxx0000 for
            // negative simm16 (high bit set). When this value flows into
            // a 64-bit subfc against a zero-extended lwz value, the unsigned
            // 64-bit comparison yields wrong CA. Truncate to 32 bits to
            // simulate 32-bit ABI behavior.
            let ra_val = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let result = ra_val.wrapping_add((instr.simm16() as i64 as u64) << 16);
            ctx.gpr[instr.rd()] = result as u32 as u64;
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **`RA0` semantics.** When the `RA` field encodes 0, the operand is the literal 64-bit zero, **not** `r0`. This makes `addis RT, 0, hi16` the canonical "load high half" idiom. To use `r0`'s actual value as a base, copy it via `mr` first or use a different opcode.
- **Immediate is sign-extended *then* shifted left 16.** So `addis r3, 0, 0x8000` writes `0xFFFFFFFF80000000`, not `0x000000008000_0000`. The 32-bit sign extension surprise is the most common bug in hand-written PPC assembly.
- **Forms the high half of a 32-bit immediate.** The classic `lis rT, hi; ori rT, rT, lo` (or `lis`/`addi`) sequence builds a full 32-bit constant. `lis rT, val` is a simplified mnemonic for `addis rT, 0, val`.
- **No `XER[CA]`, no `XER[OV]`, no `Rc`.** This instruction has no status side-effects whatsoever. Use [`addic`](addic.md) or [`addcx`](addcx.md) if a carry is required.
- **64-bit `RA` operand.** The shift-and-add is 64-bit on the Xenon; the immediate's sign-extension fills the high 48 bits. So `addis r3, r4, -1` adds `0xFFFFFFFFFFFF0000` to a 64-bit `r4`.
- **No overflow detection.** `lis r3, 0x7FFF; addis r3, r3, 0x7FFF` happily wraps without comment.

## Related Instructions

- [`addi`](addi.md) — D-form add immediate, no shift; same `RA0` rule.
- [`addic`](addic.md), [`addicx`](addicx.md) — immediate adds that also write `XER[CA]`.
- [`oris`](oris.md), [`ori`](ori.md) — pair with `addis`/`lis` to build 32-bit constants without affecting CR or XER.
- [`addx`](addx.md), [`addcx`](addcx.md) — XO-form register adds.
- `lis` (simplified) — assembler shorthand for `addis RT, 0, value`.

## IBM Reference

- [AIX 7.3 — `addis` (Add Immediate Shifted)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-addis-add-immediate-shifted-instruction)
- [AIX 7.3 — `lis` (Load Immediate Shifted, simplified mnemonic)](https://www.ibm.com/docs/en/aix/7.3.0?topic=mnemonics-li-lis-load-immediate-load-immediate-shifted)