xenia-rs/migration/project-root/ppc-manual/alu/andix.md

andi. — AND Immediate

Category: Integer ALU · Form: D · Opcode: 0x70000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
andi.	andi.	—	AND Immediate

Syntax

andi. [RA], [RS], [UIMM]

Encoding

andi. — form D

• Opcode word: 0x70000000
• Primary opcode (bits 0–5): 28
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
RS	andi.: read	Source GPR (alias for RD in some stores).
UIMM	andi.: read	16-bit unsigned immediate. Zero-extended.
RA	andi.: write	Source GPR (r0–r31).
CR	andi.: write	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

andi.

• Reads (always): RS, UIMM
• Reads (conditional): none
• Writes (always): RA, CR
• Writes (conditional): none

Status-Register Effects

• andi.: CR0 ← signed-compare(result, 0) with SO ← XER[SO] (always).

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

andi.

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="andi."
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:657
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:9
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:351
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:499-504

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::andix => {
            // PPCBUG-020: 32-bit ABI CR0 view.
            ctx.gpr[instr.ra()] = ctx.gpr[instr.rs()] & (instr.uimm16() as u64);
            ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Always Rc=1. There is no andi (without the dot). The mnemonic is andi. and the encoding always updates CR0. If you need a non-record AND-with-immediate, you have to materialise the immediate first (e.g. with li/lis) and use andx.
• Immediate is zero-extended. The 16-bit UIMM is widened with zeros, so andi. rA, rS, 0xFFFF masks rS to its low 16 bits — the high 48 bits of the 64-bit register are forced to zero.
• Cannot mask the high half of a register in one instruction. The immediate covers bits 48–63 only; for higher bits use andisx (covers bits 32–47) or compose with rlwinm/rldicl.
• CR0 update is unconditional. This is part of the encoding, not a flag — the primary opcode (28) is andi..
• Common idiom: andi. r0, rN, mask to test bits without disturbing the source — but note r0 is overwritten and CR0 is set. If you only need the CR result, prefer extrwi/rlwinm. for arbitrary masks.
• 64-bit CR update on Xenon, 32-bit in xenia-rs. Since the AND result has zeros in bits 0–47, the low-32 truncation in interpreter.rs:321 is harmless here — the result fits in 16 bits, so spec and xenia agree.

Related Instructions

• andisx — same op with immediate shifted left 16 (covers bits 32–47).
• andx, andcx — register AND family.
• ori, oris, xori, xoris — sister immediate logicals (notably without a record form).
• rlwinmx — for masks that don't fit into a 16-bit immediate.

IBM Reference

• AIX 7.3 — andi. (AND Immediate)