xenia-rs/migration/project-root/ppc-manual/alu/cmpi.md

# `cmpi` — Compare Immediate

> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0x2c000000`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `cmpi` | `cmpi` | — | Compare Immediate |

## Syntax

```asm
cmpi [CRFD], [L], [RA], [SIMM]
```

## Encoding

### `cmpi` — form `D`

- **Opcode word:** `0x2c000000`
- **Primary opcode (bits 0–5):** `11`
- **Extended opcode:** —
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS when storing) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `L` | cmpi: read | Operand-length bit for compare instructions (`0 ⇒ 32-bit`, `1 ⇒ 64-bit`). |
| `RA` | cmpi: read | Source GPR (`r0`–`r31`). |
| `SIMM` | cmpi: read | 16-bit signed immediate. Sign-extended to 64 bits before use. |
| `RD` | cmpi: write | Destination GPR. |
| `CRFD` | cmpi: write | CR destination field (`crf`, 0–7). |

## Register Effects

### `cmpi`

- **Reads (always):** `L`, `RA`, `SIMM`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`, `CRFD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
if L = 0 then a,b <- EXTS((RA)[32:63]), EXTS(SIMM)
else             a,b <- (RA), EXTS(SIMM)
CR[BF] <- signed_compare(a, b) || XER[SO]
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`cmpi`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="cmpi"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:552`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_alu.cc#L552)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:13`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L13)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:335`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L335)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:824-849`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L824-L849)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::cmpi => {
            let bf = instr.crfd();
            if instr.l() {
                // 64-bit compare. Compare directly so boundary i64 values
                // (e.g. ra=i64::MIN, imm=1) don't mis-sign through a
                // wrapped subtract.
                let ra = ctx.gpr[instr.ra()] as i64;
                let imm = instr.simm16() as i64;
                ctx.cr[bf] = crate::context::CrField {
                    lt: ra < imm,
                    gt: ra > imm,
                    eq: ra == imm,
                    so: ctx.xer_so != 0,
                };
            } else {
                let ra = ctx.gpr[instr.ra()] as i32;
                let imm = instr.simm16() as i32;
                ctx.cr[bf] = crate::context::CrField {
                    lt: ra < imm,
                    gt: ra > imm,
                    eq: ra == imm,
                    so: ctx.xer_so != 0,
                };
            }
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Immediate is sign-extended.** `SIMM` is treated as a signed 16-bit value in the range `[-32768, 32767]` and sign-extended to the operand width. Use [`cmpli`](cmpli.md) for unsigned comparisons against a 16-bit value.
- **`L` bit selects width.** `L = 0` (the usual `cmpwi`) compares the low 32 bits of `RA` (sign-extended) against `EXTS(SIMM)`; `L = 1` (`cmpdi`) does a full 64-bit signed compare. Most Xbox 360 code uses `cmpwi` because pointers and counters are 32-bit ABI.
- **Simplified mnemonics dominate disassembly.** `cmpwi crN, RA, SIMM` ≡ `cmpi crN, 0, RA, SIMM` and `cmpdi crN, RA, SIMM` ≡ `cmpi crN, 1, RA, SIMM`. The default CR field is `cr0` if omitted.
- **`BF` is a CR field (0–7), not a bit.** Same convention as [`cmp`](cmp.md). Distinct standalone compares should target `cr1..cr7` to avoid clobbering the implicit `cr0` chain set up by `Rc=1` arithmetic.
- **SO is copied from `XER[SO]`.** This makes overflow observable downstream of an `addo.` / `mulo.` etc. via `bso`/`bns`.
- **Xenia-rs quirk.** The interpreter recomputes `EQ` after the signed subtract, defending against the same 32-bit narrowing edge case noted in [`cmp`](cmp.md). Functionally equivalent to spec.
- **No register written** other than the 4-bit CR field — there is no `Rc` or `OE` bit.

## Related Instructions

- [`cmp`](cmp.md) — register-register signed compare.
- [`cmpli`](cmpli.md) — unsigned compare against immediate (zero-extended).
- [`cmpl`](cmpl.md) — unsigned register compare.
- `cmpwi`, `cmpdi` (simplified mnemonics) — select `L=0` / `L=1`.
- [`mcrxr`](mcrxr.md) — clear sticky overflow before a fresh compare sequence.

## IBM Reference

- [AIX 7.3 — `cmpi` (Compare Immediate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-cmpi-compare-immediate-instruction)
- [AIX 7.3 — `cmpwi` / `cmpdi` (simplified mnemonics)](https://www.ibm.com/docs/en/aix/7.3.0?topic=mnemonics-cmpwi-compare-word-immediate)