xenia-rs/migration/project-root/ppc-manual/alu/cmpli.md

cmpli — Compare Logical Immediate

Category: Integer ALU · Form: D · Opcode: 0x28000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
cmpli	cmpli	—	Compare Logical Immediate

Syntax

cmpli [CRFD], [L], [RA], [UIMM]

Encoding

cmpli — form D

• Opcode word: 0x28000000
• Primary opcode (bits 0–5): 10
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
L	cmpli: read	Operand-length bit for compare instructions (0 ⇒ 32-bit, 1 ⇒ 64-bit).
RA	cmpli: read	Source GPR (r0–r31).
UIMM	cmpli: read	16-bit unsigned immediate. Zero-extended.
CRFD	cmpli: write	CR destination field (crf, 0–7).

Register Effects

cmpli

• Reads (always): L, RA, UIMM
• Reads (conditional): none
• Writes (always): CRFD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

if L = 0 then a,b <- (RA)[32:63], UIMM
else             a,b <- (RA), (0 || UIMM)
CR[BF] <- unsigned_compare(a, b) || XER[SO]

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

cmpli

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="cmpli"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:608
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:13
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:334
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:850-862

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::cmpli => {
            let bf = instr.crfd();
            if instr.l() {
                let ra = ctx.gpr[instr.ra()];
                let imm = instr.uimm16() as u64;
                ctx.update_cr_unsigned(bf, ra, imm);
            } else {
                let ra = ctx.gpr[instr.ra()] as u32 as u64;
                let imm = instr.uimm16() as u64;
                ctx.update_cr_unsigned(bf, ra, imm);
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Immediate is zero-extended. UIMM is a 16-bit value extended with zeros, so the comparable range is [0, 65535]. To compare against a value with high bits set, materialise it in a register with lis/ori and use cmpl.
• L bit selects width. L = 0 (cmplwi) zero-extends RA[32:63] to 64 bits and compares against the 16-bit immediate (also zero-extended). L = 1 (cmpldi) compares the full 64-bit RA against the immediate.
• Simplified mnemonics dominate. cmplwi cr0, RA, UIMM ≡ cmpli cr0, 0, RA, UIMM; the assembler injects the L bit automatically.
• No sign-extension surprises. Unlike cmpi, the immediate cannot be negative; cmpli always tests an unsigned magnitude.
• Common idiom: cmplwi rA, 0 to test a register for zero — slightly clearer in disassembly than cmpwi rA, 0 because it doesn't suggest signed semantics. Both produce the same EQ result for a zero argument.
• BF chooses one of 8 CR fields; same convention as cmp.

Related Instructions

• cmpl — register-register unsigned compare.
• cmpi — signed compare against a 16-bit immediate.
• cmp — register-register signed compare.
• cmplwi, cmpldi (simplified) — most common form seen in disassembly.

IBM Reference

• AIX 7.3 — cmpli (Compare Logical Immediate)
• AIX 7.3 — cmplwi / cmpldi (simplified mnemonics)