e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
121 lines
5.0 KiB
Markdown
121 lines
5.0 KiB
Markdown
# `mulli` — Multiply Low Immediate
|
||
|
||
> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0x1c000000`
|
||
|
||
<!-- GENERATED: BEGIN -->
|
||
|
||
## Assembler Mnemonics
|
||
|
||
| Mnemonic | XML entry | Flags | Description |
|
||
| --- | --- | --- | --- |
|
||
| `mulli` | `mulli` | — | Multiply Low Immediate |
|
||
|
||
## Syntax
|
||
|
||
```asm
|
||
mulli [RD], [RA], [SIMM]
|
||
```
|
||
|
||
## Encoding
|
||
|
||
### `mulli` — form `D`
|
||
|
||
- **Opcode word:** `0x1c000000`
|
||
- **Primary opcode (bits 0–5):** `7`
|
||
- **Extended opcode:** —
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode |
|
||
| 6–10 | `RT` | destination GPR (or RS when storing) |
|
||
| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
|
||
| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
|
||
|
||
## Operands
|
||
|
||
| Field | Role | Description |
|
||
| --- | --- | --- |
|
||
| `RA` | mulli: read | Source GPR (`r0`–`r31`). |
|
||
| `SIMM` | mulli: read | 16-bit signed immediate. Sign-extended to 64 bits before use. |
|
||
| `RD` | mulli: write | Destination GPR. |
|
||
|
||
## Register Effects
|
||
|
||
### `mulli`
|
||
|
||
- **Reads (always):** `RA`, `SIMM`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** `RD`
|
||
- **Writes (conditional):** _none_
|
||
|
||
## Status-Register Effects
|
||
|
||
_No condition-register or status-register effects._
|
||
|
||
## Operation (pseudocode)
|
||
|
||
```
|
||
RT <- ((RA) * EXTS(SIMM))[64:127]
|
||
```
|
||
|
||
## C Translation Example
|
||
|
||
```c
|
||
/* C translation: the xenia-rs interpreter arm below in */
|
||
/* Implementation References is the authoritative semantic */
|
||
/* snapshot. Translate it line-by-line: */
|
||
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
|
||
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
|
||
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
|
||
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
|
||
/* The Register Effects and Status-Register Effects tables above */
|
||
/* enumerate every side effect a faithful translation must emit. */
|
||
```
|
||
|
||
## Implementation References
|
||
|
||
**`mulli`**
|
||
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="mulli"`](../../xenia-canary/tools/ppc-instructions.xml)
|
||
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:382`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_alu.cc#L382)
|
||
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:57`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L57)
|
||
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:332`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L332)
|
||
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:165-172`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L165-L172)
|
||
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
|
||
|
||
```rust
|
||
PpcOpcode::mulli => {
|
||
// PPCBUG-004: 32-bit ABI. Read RA as i32 (low 32, sign-extended for
|
||
// multiply), product fits in 32 bits per ISA (overflow wraps).
|
||
let ra = ctx.gpr[instr.ra()] as i32 as i64;
|
||
let imm = instr.simm16() as i64;
|
||
ctx.gpr[instr.rd()] = (ra.wrapping_mul(imm) as u32) as u64;
|
||
ctx.pc += 4;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
<!-- GENERATED: END -->
|
||
|
||
## Special Cases & Edge Conditions
|
||
|
||
- **64-bit operand, sign-extended 16-bit immediate.** Xenia reads the full 64-bit `RA` as `i64` and the immediate as a sign-extended `i64` ([`interpreter.rs:80-81`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L80-L81)) — note this differs from the PPC pseudocode header which writes `(RA) * EXTS(SIMM)` as a 64-bit operation but other implementations sometimes treat it as 32×32. On the Xenon (and in xenia-rs), it is genuinely 64-bit.
|
||
- **Returns the low 64 bits.** No high half is produced — equivalent to `(int64_t)RA * (int64_t)SIMM` modulo `2^64`. There is no `mulhi`-immediate instruction.
|
||
- **No `Rc`, no `OE`.** This D-form has no flag bits — strictly `RT ← RA * SIMM`. To check overflow, compare the result to `(int32_t)RA * SIMM` after the fact, or use [`mulldx`](mulldx.md) with `OE=1` after materialising the immediate.
|
||
- **Common compiler idiom.** `mulli` is heavily used for fixed-stride array indexing (`r3 *= sizeof_struct`) when the size is a small signed constant.
|
||
- **No carry.** `XER[CA]` is untouched.
|
||
- **Same multi-cycle latency** as `mullw` / `mulld`. Compilers strength-reduce `mulli rD, rA, 2^k` to a left shift and `mulli rD, rA, 3` to `add+shift` when the immediate has cheap structure.
|
||
- **Aliasing fine.** `mulli r3, r3, 5` rewrites in place.
|
||
|
||
## Related Instructions
|
||
|
||
- [`mullwx`](mullwx.md) — register-register low 32 (signed).
|
||
- [`mulldx`](mulldx.md) — register-register low 64 (signed).
|
||
- [`mulhdx`](mulhdx.md), [`mulhdux`](mulhdux.md) — high halves (no immediate variant).
|
||
- [`addi`](addi.md) — add immediate; sometimes substituted by compilers when the multiplier is `2^k+1` etc.
|
||
- [`slwx`](slwx.md), [`sldx`](sldx.md) — shifts often replace `mulli` for power-of-two multipliers.
|
||
|
||
## IBM Reference
|
||
|
||
- [AIX 7.3 — `mulli` (Multiply Low Immediate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-mulli-multiply-low-immediate-instruction)
|