xenia-rs/migration/project-root/ppc-manual/alu/ori.md

ori — OR Immediate

Category: Integer ALU · Form: D · Opcode: 0x60000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
ori	ori	—	OR Immediate

Syntax

ori [RA], [RS], [UIMM]

Encoding

ori — form D

• Opcode word: 0x60000000
• Primary opcode (bits 0–5): 24
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
RS	ori: read	Source GPR (alias for RD in some stores).
UIMM	ori: read	16-bit unsigned immediate. Zero-extended.
RA	ori: write	Source GPR (r0–r31).

Register Effects

ori

• Reads (always): RS, UIMM
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

RA <- (RS) | (0x0000 || UIMM)

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

ori

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="ori"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:810
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:59
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:347
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:512-515

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::ori => {
            ctx.gpr[instr.ra()] = ctx.gpr[instr.rs()] | (instr.uimm16() as u64);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• No record form. Unlike andix, ori does not update CR0 — there is no ori.. If you need a CR update after OR-immediate, follow it with cmpwi or use orx with Rc=1.
• Immediate is zero-extended. Only the low 16 bits of RA can be affected; the high 48 bits are passed through from RS unchanged.
• ori 0, 0, 0 is the canonical NOP. All PowerPC NOPs assemble to this encoding (0x60000000). Disassemblers usually display this as nop.
• Common idiom: build a 32-bit constant via lis + ori. lis r3, hi16; ori r3, r3, lo16 materialises any 32-bit immediate with no CR or XER disturbance.
• 64-bit operation in xenia-rs. interpreter.rs:330 — full u64 OR; high bits unchanged from RS.
• RA = 0 reads r0 (not the literal zero). Different from addi's RA0 semantics; ori uses the regular RA interpretation.

Related Instructions

• oris — same op with the immediate shifted left 16.
• orx — register-register; supports Rc=1.
• xori, xoris, andix, andisx — sister immediate logicals.
• nop (simplified) — ori 0, 0, 0.

IBM Reference

• AIX 7.3 — ori (OR Immediate)
• AIX 7.3 — nop (simplified)