xenia-rs/migration/project-root/ppc-manual/alu/rldiclx.md

rldiclx — Rotate Left Doubleword Immediate then Clear Left

Category: Integer ALU · Form: MD · Opcode: 0x78000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rldicl	rldiclx	—	Rotate Left Doubleword Immediate then Clear Left
rldicl.	rldiclx	Rc=1	Rotate Left Doubleword Immediate then Clear Left

Syntax

rldicl[Rc] [RA], [RS], [SH], [MB]

Encoding

rldiclx — form MD

• Opcode word: 0x78000000
• Primary opcode (bits 0–5): 30
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (30)
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	sh	shift amount low 5 bits
21–26	mb/me	6-bit mask field (swapped halves)
27–29	XO	extended opcode
30	sh5	shift amount high bit
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rldiclx: read	Source GPR (alias for RD in some stores).
SH	rldiclx: read	Shift amount.
MB	rldiclx: read	Mask begin bit.
RA	rldiclx: write	Source GPR (r0–r31).
CR	rldiclx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rldiclx

• Reads (always): RS, SH, MB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rldiclx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rldiclx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="rldiclx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:929
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:61
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:728
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:762-771

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::rldiclx => {
            let rs = ctx.gpr[instr.rs()];
            let sh = instr.sh64();
            let mb = instr.mb_md();
            let rotated = rs.rotate_left(sh);
            let mask = rld_mask_left(mb);
            ctx.gpr[instr.ra()] = rotated & mask;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• RA ← ROTL64(RS, SH) & MASK(MB, 63). Rotate left by SH, then clear bits 0 through MB-1. The mask retains bits MB..63.
• The Swiss-army knife of bit extraction. Many assembler shorthands lower to this single instruction:
  • srdi RA, RS, n ≡ rldicl RA, RS, 64-n, n — logical right shift by n.
  • clrldi RA, RS, n ≡ rldicl RA, RS, 0, n — clear top n bits.
  • extrdi RA, RS, n, b ≡ rldicl RA, RS, b+n, 64-n — extract n bits starting at b.
• SH is 6 bits, immediate (bits 16–20 + bit 30). Xenia uses instr.sh64() to assemble them.
• MB is 6 bits, split-encoded ((instr.mb() << 1) | ((raw >> 1) & 1)).
• Rc=1 CR0 is correctly 64-bit. Uses as i64 directly (interpreter.rs:551).
• No XER effect.
• Often appears in compiled disassembly as a generic 64-bit shift. Decoding back to the simplified mnemonic above makes the intent obvious.

Related Instructions

• rldicrx — clear-right counterpart (MASK(0, ME)).
• rldicx — clear both ends.
• rldclx — register-shift version.
• rlwinmx — 32-bit cousin.
• srdi, clrldi, extrdi (simplified mnemonics).

IBM Reference

• AIX 7.3 — rldicl (Rotate Left Doubleword Immediate then Clear Left)
• AIX 7.3 — Simplified shift/extract mnemonics