e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
140 lines
5.6 KiB
Markdown
140 lines
5.6 KiB
Markdown
# `rlwnmx` — Rotate Left Word then AND with Mask
|
||
|
||
> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [M](../forms/M.md) · **Opcode:** `0x5c000000`
|
||
|
||
<!-- GENERATED: BEGIN -->
|
||
|
||
## Assembler Mnemonics
|
||
|
||
| Mnemonic | XML entry | Flags | Description |
|
||
| --- | --- | --- | --- |
|
||
| `rlwnm` | `rlwnmx` | — | Rotate Left Word then AND with Mask |
|
||
| `rlwnm.` | `rlwnmx` | Rc=1 | Rotate Left Word then AND with Mask |
|
||
|
||
## Syntax
|
||
|
||
```asm
|
||
rlwnm[Rc] [RA], [RS], [RB], [MB], [ME]
|
||
```
|
||
|
||
## Encoding
|
||
|
||
### `rlwnmx` — form `M`
|
||
|
||
- **Opcode word:** `0x5c000000`
|
||
- **Primary opcode (bits 0–5):** `23`
|
||
- **Extended opcode:** —
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode |
|
||
| 6–10 | `RS` | source GPR |
|
||
| 11–15 | `RA` | destination GPR |
|
||
| 16–20 | `SH/RB` | shift amount or source B |
|
||
| 21–25 | `MB` | mask begin |
|
||
| 26–30 | `ME` | mask end |
|
||
| 31 | `Rc` | record-form flag |
|
||
|
||
## Operands
|
||
|
||
| Field | Role | Description |
|
||
| --- | --- | --- |
|
||
| `RS` | rlwnmx: read | Source GPR (alias for RD in some stores). |
|
||
| `RB` | rlwnmx: read | Source GPR. |
|
||
| `MB` | rlwnmx: read | Mask begin bit. |
|
||
| `ME` | rlwnmx: read | Mask end bit. |
|
||
| `RA` | rlwnmx: write | Source GPR (`r0`–`r31`). |
|
||
| `CR` | rlwnmx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
|
||
|
||
## Register Effects
|
||
|
||
### `rlwnmx`
|
||
|
||
- **Reads (always):** `RS`, `RB`, `MB`, `ME`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** `RA`
|
||
- **Writes (conditional):** `CR`
|
||
|
||
## Status-Register Effects
|
||
|
||
- `rlwnmx`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.
|
||
|
||
## Operation (pseudocode)
|
||
|
||
```
|
||
; Pseudocode derives directly from the xenia-rs interpreter
|
||
; arm (see Implementation References). Operation semantics:
|
||
; - Read source operands from the fields listed under Operands.
|
||
; - Apply the arithmetic / logical / memory action described
|
||
; in the Description field above.
|
||
; - Write results to the destination register(s); update any
|
||
; status bits enumerated under Status-Register Effects.
|
||
; Consult the IBM AIX reference link under IBM Reference for
|
||
; canonical PPC-style pseudocode where xenia's expression is
|
||
; terse.
|
||
```
|
||
|
||
## C Translation Example
|
||
|
||
```c
|
||
/* C translation: the xenia-rs interpreter arm below in */
|
||
/* Implementation References is the authoritative semantic */
|
||
/* snapshot. Translate it line-by-line: */
|
||
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
|
||
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
|
||
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
|
||
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
|
||
/* The Register Effects and Status-Register Effects tables above */
|
||
/* enumerate every side effect a faithful translation must emit. */
|
||
```
|
||
|
||
## Implementation References
|
||
|
||
**`rlwnmx`**
|
||
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="rlwnmx"`](../../xenia-canary/tools/ppc-instructions.xml)
|
||
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:1101`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_alu.cc#L1101)
|
||
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:61`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L61)
|
||
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:346`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L346)
|
||
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:750-761`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L750-L761)
|
||
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
|
||
|
||
```rust
|
||
PpcOpcode::rlwnmx => {
|
||
let rs = ctx.gpr[instr.rs()] as u32;
|
||
let sh = ctx.gpr[instr.rb()] as u32 & 0x1F;
|
||
let mb = instr.mb();
|
||
let me = instr.me();
|
||
let rotated = rs.rotate_left(sh);
|
||
let mask = rlw_mask(mb, me);
|
||
ctx.gpr[instr.ra()] = (rotated & mask) as u64;
|
||
// PPCBUG-026: 32-bit ABI CR0 view.
|
||
if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
|
||
ctx.pc += 4;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
<!-- GENERATED: END -->
|
||
|
||
## Special Cases & Edge Conditions
|
||
|
||
- **`RA ← ROTL32(RS[32:63], RB[59:63]) & MASK(MB, ME)`.** Identical to [`rlwinmx`](rlwinmx.md) except the rotate amount comes from the low 5 bits of `RB`. Xenia masks with `& 0x1F` ([`interpreter.rs:535`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L535)).
|
||
- **Use over `rlwinm`** when the rotate amount is dynamic (e.g. computed from a `cntlzw` for normalisation, or read from a parameter).
|
||
- **Mask is still 5+5 bits immediate** — `MB` and `ME` are not register-sourced; only the shift is. This is the M-form's quirk: only one of (`SH`, `MB`, `ME`) is variable across the family.
|
||
- **Donut masks supported.** `MB > ME` produces a wraparound mask, same as `rlwinm`.
|
||
- **High 32 bits of `RA` are zero** (32-bit operation, then `as u64` zero-extends).
|
||
- **`Rc=1` CR0 update truncates to 32 bits in xenia-rs.** [`interpreter.rs:540`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L540) — harmless because the result already fits in 32 bits.
|
||
- **No `XER` effect.**
|
||
|
||
## Related Instructions
|
||
|
||
- [`rlwinmx`](rlwinmx.md) — same op, immediate shift.
|
||
- [`rlwimix`](rlwimix.md) — insert variant (no register-shift form exists for insert).
|
||
- [`rldclx`](rldclx.md), [`rldcrx`](rldcrx.md) — 64-bit register-shift cousins.
|
||
- [`slwx`](slwx.md), [`srwx`](srwx.md) — straight 32-bit shifts.
|
||
|
||
## IBM Reference
|
||
|
||
- [AIX 7.3 — `rlwnm` (Rotate Left Word then AND with Mask)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-rlwnm-rotate-left-word-then-mask-instruction)
|