e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
125 lines
4.9 KiB
Markdown
125 lines
4.9 KiB
Markdown
# `sldx` — Shift Left Doubleword
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> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c000036`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `sld` | `sldx` | — | Shift Left Doubleword |
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| `sld.` | `sldx` | Rc=1 | Shift Left Doubleword |
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## Syntax
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```asm
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sld[Rc] [RA], [RS], [RB]
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```
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## Encoding
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### `sldx` — form `X`
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- **Opcode word:** `0x7c000036`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `27`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RS` | sldx: read | Source GPR (alias for RD in some stores). |
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| `RB` | sldx: read | Source GPR. |
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| `RA` | sldx: write | Source GPR (`r0`–`r31`). |
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| `CR` | sldx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
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## Register Effects
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### `sldx`
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- **Reads (always):** `RS`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RA`
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- **Writes (conditional):** `CR`
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## Status-Register Effects
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- `sldx`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.
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## Operation (pseudocode)
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```
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n <- (RB)[57:63]
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RA <- ((RS) << n) if n < 64 else 0
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`sldx`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="sldx"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:1122`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_alu.cc#L1122)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:65`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L65)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:759`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L759)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:676-683`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L676-L683)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::sldx => {
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let sh = ctx.gpr[instr.rb()] & 0x7F;
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ctx.gpr[instr.ra()] = if sh < 64 {
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ctx.gpr[instr.rs()] << sh
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} else { 0 };
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if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as i64); }
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **64-bit logical left shift.** `RA ← RS << (RB & 0x7F)` if the shift count is `< 64`, otherwise `RA = 0`. Bits shifted past bit 0 are discarded.
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- **Critical: shift count is *7 bits*, not 6.** PowerISA reads `RB[57:63]` (7 bits, `0..127`). Counts in `[64, 127]` produce zero, *not* `RS << (count mod 64)`. Xenia respects this with `& 0x7F` and an explicit `if sh < 64` check ([`interpreter.rs:464`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L464)). C semantics' undefined behaviour for `<<` with a count `>= width` is a spec-violation source if you naïvely translate.
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- **No `XER[CA]` produced** by left shifts. Logical right [`srdx`](srdx.md) and arithmetic right [`sradx`](sradx.md) differ here — arithmetic right *does* set `CA`.
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- **`Rc=1` CR0 is correctly 64-bit.** [`interpreter.rs:467`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L467) uses `as i64` directly. CR0 reflects the sign of the full 64-bit shifted value (which is 0 for shifts ≥ 64, otherwise either `LT`/`GT`/`EQ`).
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- **Strength-reduced from `mulli` for power-of-two multipliers.**
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- **No `OE` bit.**
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## Related Instructions
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- [`slwx`](slwx.md) — 32-bit logical left shift.
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- [`srdx`](srdx.md) — 64-bit logical right shift.
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- [`sradx`](sradx.md), [`sradix`](sradix.md) — 64-bit arithmetic right shifts.
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- [`rldicrx`](rldicrx.md) — `sldi` simplified mnemonic uses this.
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- [`mulli`](mulli.md) — for non-power-of-two multipliers.
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## IBM Reference
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- [AIX 7.3 — `sld` (Shift Left Doubleword)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-sld-shift-left-double-word-instruction)
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