xenia-rs/migration/project-root/ppc-manual/alu/sradix.md

sradix — Shift Right Algebraic Doubleword Immediate

Category: Integer ALU · Form: XS · Opcode: 0x7c000674

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
sradi	sradix	—	Shift Right Algebraic Doubleword Immediate
sradi.	sradix	Rc=1	Shift Right Algebraic Doubleword Immediate

Syntax

sradi[Rc] [RA], [RS], [SH]

Encoding

sradix — form XS

• Opcode word: 0x7c000674
• Primary opcode (bits 0–5): 31
• Extended opcode: 826
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	sh	shift amount low 5 bits
21–29	XO	extended opcode (9 bits)
30	sh5	shift amount high bit
31	Rc	record-form flag

Operands

Field	Role	Description
RS	sradix: read	Source GPR (alias for RD in some stores).
SH	sradix: read	Shift amount.
RA	sradix: write	Source GPR (r0–r31).
CR	sradix: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
CA	sradix: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.

Register Effects

sradix

• Reads (always): RS, SH
• Reads (conditional): none
• Writes (always): RA, CA
• Writes (conditional): CR

Status-Register Effects

• sradix: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

RA <- ((RS) >>a SH) sign-extended
CA <- (RS signed < 0) && any_bit_shifted_out

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

sradix

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="sradix"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:1230
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:65
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:743
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:709-722

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::sradix => {
            let rs = ctx.gpr[instr.rs()] as i64;
            let sh = instr.sh64();
            if sh == 0 {
                ctx.gpr[instr.ra()] = rs as u64;
                ctx.xer_ca = 0;
            } else {
                let result = rs >> sh;
                ctx.xer_ca = if rs < 0 && (rs as u64) << (64 - sh) != 0 { 1 } else { 0 };
                ctx.gpr[instr.ra()] = result as u64;
            }
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• RA ← (i64)RS >> SH, with XER[CA] set when RS is negative AND any one-bit was shifted out.
• SH is 6 bits. Encoded in bits 16–20 (sh) plus bit 30 (sh5); xenia uses instr.sh64() to assemble the 6 bits (interpreter.rs:496). Range 0..63.
• SH = 0 is a no-op (sign-extends RS to itself), and explicitly clears XER[CA] (interpreter.rs:498). This matches spec.
• Spec divergence: 6-bit immediate, no saturation arm. Unlike sradx which has a 7-bit register count and saturates at ≥ 64, sradi always uses a count < 64 so no special saturation case is needed.
• Rc=1 CR0 is correctly 64-bit. interpreter.rs:506.
• Idiom: sradi rA, rS, n; addze rA, rA — signed integer divide by 2^n rounded toward zero (the textbook PPC sequence).
• No OE bit.

Related Instructions

• sradx — register-shift form.
• srawix, srawx — 32-bit arithmetic right.
• addzex — pair for signed-divide-rounding.
• rldiclx — when arithmetic semantics not required (logical shift), srdi simplified mnemonic.

IBM Reference

• AIX 7.3 — sradi (Shift Right Algebraic Doubleword Immediate)