xenia-rs/migration/project-root/ppc-manual/alu/sradx.md

sradx — Shift Right Algebraic Doubleword

Category: Integer ALU · Form: X · Opcode: 0x7c000634

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
srad	sradx	—	Shift Right Algebraic Doubleword
srad.	sradx	Rc=1	Shift Right Algebraic Doubleword

Syntax

srad[Rc] [RA], [RS], [RB]

Encoding

sradx — form X

• Opcode word: 0x7c000634
• Primary opcode (bits 0–5): 31
• Extended opcode: 794
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	sradx: read	Source GPR (alias for RD in some stores).
RB	sradx: read	Source GPR.
RA	sradx: write	Source GPR (r0–r31).
CR	sradx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
CA	sradx: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.

Register Effects

sradx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA, CA
• Writes (conditional): CR

Status-Register Effects

• sradx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

n <- (RB)[57:63]
RA <- ((RS) >>a n) sign-extended        if n < 64
CA <- (RS signed < 0) && any_bit_shifted_out

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

sradx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="sradx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:1201
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:65
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:841
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:692-708

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::sradx => {
            let rs = ctx.gpr[instr.rs()] as i64;
            let sh = ctx.gpr[instr.rb()] & 0x7F;
            if sh == 0 {
                ctx.gpr[instr.ra()] = rs as u64;
                ctx.xer_ca = 0;
            } else if sh < 64 {
                let result = rs >> sh;
                ctx.xer_ca = if rs < 0 && (rs as u64) << (64 - sh) != 0 { 1 } else { 0 };
                ctx.gpr[instr.ra()] = result as u64;
            } else {
                ctx.gpr[instr.ra()] = if rs < 0 { u64::MAX } else { 0 };
                ctx.xer_ca = if rs < 0 { 1 } else { 0 };
            }
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• 64-bit arithmetic (sign-propagating) right shift. RA ← (i64)RS >> (RB & 0x7F) with bits shifted in matching the sign bit of RS. Counts ≥ 64 saturate: RA becomes all-ones if RS < 0, else zero.
• XER[CA] is the "lost-ones" indicator. CA = 1 iff RS is negative AND any of the bits shifted out were 1. This makes srad / sradi the standard idiom for "divide negative integer by power of 2 with round-toward-zero" — followed by addze to compensate when CA = 1.
• Three branches in xenia. sh == 0 (no shift, CA=0), sh < 64 (normal shift, CA per spec), and sh ≥ 64 (saturate to 0 or −1, CA reflects sign). The (rs as u64) << (64 - sh) != 0 check at interpreter.rs:486 extracts whether any non-zero bit was shifted out.
• Shift count is 7 bits. Same as sldx: RB[57:63].
• Rc=1 CR0 is correctly 64-bit. interpreter.rs:489.
• No OE bit.
• Used by signed-divide-by-power-of-2 idiom: srad rA, rS, n; addze rA, rA produces rS / 2^n with truncation toward zero rather than toward -∞.

Related Instructions

• sradix — immediate-shift form (SH 6-bit immediate).
• srawx, srawix — 32-bit arithmetic right shifts.
• srdx — 64-bit logical right shift (no XER[CA]).
• addzex — companion for the divide-rounding idiom.
• sldx — left shift.

IBM Reference

• AIX 7.3 — srad (Shift Right Algebraic Doubleword)