Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
5.8 KiB
5.8 KiB
subfx — Subtract From
Category: Integer ALU · Form: XO · Opcode:
0x7c000050
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
subf |
subfx |
— | Subtract From |
subfo |
subfx |
OE=1 | Subtract From |
subf. |
subfx |
Rc=1 | Subtract From |
subfo. |
subfx |
OE=1, Rc=1 | Subtract From |
Syntax
subf[OE][Rc] [RD], [RA], [RB]
Encoding
subfx — form XO
- Opcode word:
0x7c000050 - Primary opcode (bits 0–5):
31 - Extended opcode:
40 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (31) |
| 6–10 | RT |
destination GPR |
| 11–15 | RA |
source A |
| 16–20 | RB |
source B |
| 21 | OE |
overflow-enable flag |
| 22–30 | XO |
extended opcode (9 bits) |
| 31 | Rc |
record-form flag |
Operands
| Field | Role | Description |
|---|---|---|
RA |
subfx: read | Source GPR (r0–r31). |
RB |
subfx: read | Source GPR. |
RD |
subfx: write | Destination GPR. |
CR |
subfx: write (conditional) | Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
OE |
subfx: write (conditional) | Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow. |
Register Effects
subfx
- Reads (always):
RA,RB - Reads (conditional): none
- Writes (always):
RD - Writes (conditional):
CR,OE
Status-Register Effects
subfx: CR0 ← signed-compare(result, 0) withSO ← XER[SO], whenRc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, whenOE=1.
Operation (pseudocode)
RT <- ~(RA) + (RB) + 1 ; = (RB) − (RA)
C Translation Example
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
subfx
- xenia-canary XML:
tools/ppc-instructions.xml— search formnem="subfx" - xenia-canary emit:
src/xenia/cpu/ppc/ppc_emit_alu.cc:427 - xenia-rs opcode:
crates/xenia-cpu/src/opcode.rs:83 - xenia-rs decoder:
crates/xenia-cpu/src/decoder.rs:863 - xenia-rs interpreter:
crates/xenia-cpu/src/interpreter.rs:255-269
xenia-rs interpreter body (frozen snapshot)
PpcOpcode::subfx => {
// PPCBUG-017+020: 32-bit truncation.
let ra32 = ctx.gpr[instr.ra()] as u32;
let rb32 = ctx.gpr[instr.rb()] as u32;
let result32 = rb32.wrapping_sub(ra32);
ctx.gpr[instr.rd()] = result32 as u64;
if instr.oe() {
let true_diff = (rb32 as i32 as i128) - (ra32 as i32 as i128);
overflow::apply(ctx, true_diff != (result32 as i32) as i128);
}
if instr.rc_bit() {
ctx.update_cr_signed(0, result32 as i32 as i64);
}
ctx.pc += 4;
}
Extended Pseudocode
RT <- ~(RA) + (RB) + 1 ; = (RB) − (RA)
if OE then
XER[OV] <- signed_overflow_of_subtract((RB), (RA), RT)
XER[SO] <- XER[SO] | XER[OV]
if Rc then
CR0[LT,GT,EQ] <- signed_compare(RT, 0)
CR0[SO] <- XER[SO]
Special Cases & Edge Conditions
- Operand order gotcha.
subf RT, RA, RBcomputesRT ← RB − RA, notRA − RB. This reverses the intuitive ordering seen in x86/ARM. The assembler exposes a simplified mnemonicsub RT, RX, RY≡subf RT, RY, RXthat restores the natural order — watch for both forms in disassembly. - Implemented as add-with-complement. Hardware (and xenia) compute
~RA + RB + 1. All overflow/CR semantics are the same asaddxwith one operand complemented. - No
XER[CA]update — usesubfcxif you need a borrow-out bit. - No trap on overflow.
subfo/subfo.only record the event inXER[OV]and sticky-setXER[SO]. - Signed-overflow predicate.
OV = ((RA ^ RB) & (RB ^ RT)) >> 63— set when operands have different signs and the result's sign differs fromRB's. - 64-bit CR update on Xenon (xenia-rs truncates to 32 bits; see
addxnote).
Related Instructions
subfcx— subtract-from producingXER[CA](borrow-out).subfex—~RA + RB + XER[CA](subtract-with-borrow chain).subfmex,subfzex— subtract-from−1/0with carry-in (propagates borrows).subfic— D-form:RT ← SIMM − RAwithXER[CA].negx— specialises to0 − RA.addx— inverse; shares overflow machinery.