xenia-rs/migration/project-root/ppc-manual/control/creqv.md

creqv — Condition Register Equivalent

Category: Control / CR / SPR · Form: XL · Opcode: 0x4c000242

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
creqv	creqv	—	Condition Register Equivalent

Syntax

creqv [CRBD], [CRBA], [CRBB]

Encoding

creqv — form XL

• Opcode word: 0x4c000242
• Primary opcode (bits 0–5): 19
• Extended opcode: 289
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (19)
6–10	BT/BO	target / branch options
11–15	BA/BI	source A / CR bit to test
16–20	BB	source B
21–30	XO	extended opcode (10 bits)
31	LK	link flag

Operands

Field	Role	Description
CRBA	creqv: read	CR source bit A (0–31).
CRBB	creqv: read	CR source bit B (0–31).
CRBD	creqv: write	CR destination bit (0–31).

Register Effects

creqv

• Reads (always): CRBA, CRBB
• Reads (conditional): none
• Writes (always): CRBD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

creqv

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="creqv"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_control.cc:370
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:17
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:718

Special Cases & Edge Conditions

• Operation. CR[CRBD] ← ¬(CR[CRBA] XOR CR[CRBB]) — i.e. logical equivalence (XNOR). Result is 1 iff CRBA and CRBB agree.
• crset BT idiom. With identical operands, creqv BT, BT, BT always yields 1 (any bit XNOR'd with itself is 1). This is the canonical PowerPC set-to-1 for a single CR bit; assemblers recognise the simplified mnemonic crset BT.
• Bit-level operands. Like all CR-logical ops, the three operands are 5-bit absolute CR-bit indices (0..31). Mixing CR fields is fine.
• Use case. Branch on "A == B" of two prior compare results. Example: crxor of CR0.SO and CR1.SO gives "differ"; creqv gives "agree".
• No Rc / OE. Doesn't touch CR0, XER, or any other state beyond the named bit.
• Not synchronising. Reorderable.
• xenia status. Interpreter dispatches through the generic CR-logical helper; canary emits the host XNOR equivalent. The crset simplified form is the most common occurrence in real Xbox 360 code.

Related Instructions

• crand, crandc — AND family.
• cror, crorc, crnor, crnand — OR family.
• crxor — the dual; crxor BT, BT, BT is the standard clear-to-0 idiom.
• mcrf — bulk CR-field move.
• bcx — consumes the synthesised bit.

Simplified Mnemonics

Simplified	Expansion	Effect
crset BT	creqv BT, BT, BT	force CR[BT] ← 1

IBM Reference

• AIX 7.3 — creqv (Condition Register Equivalent)
• AIX 7.3 — Condition register simplified mnemonics