xenia-rs/migration/project-root/ppc-manual/control/cror.md

cror — Condition Register OR

Category: Control / CR / SPR · Form: XL · Opcode: 0x4c000382

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
cror	cror	—	Condition Register OR

Syntax

cror [CRBD], [CRBA], [CRBB]

Encoding

cror — form XL

• Opcode word: 0x4c000382
• Primary opcode (bits 0–5): 19
• Extended opcode: 449
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (19)
6–10	BT/BO	target / branch options
11–15	BA/BI	source A / CR bit to test
16–20	BB	source B
21–30	XO	extended opcode (10 bits)
31	LK	link flag

Operands

Field	Role	Description
CRBA	cror: read	CR source bit A (0–31).
CRBB	cror: read	CR source bit B (0–31).
CRBD	cror: write	CR destination bit (0–31).

Register Effects

cror

• Reads (always): CRBA, CRBB
• Reads (conditional): none
• Writes (always): CRBD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

cror

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="cror"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_control.cc:397
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:17
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:720

Special Cases & Edge Conditions

• Operation. CR[CRBD] ← CR[CRBA] OR CR[CRBB]. All other CR bits are preserved.
• crmove BT, BA idiom. With BA == BB, cror BT, BA, BA is the canonical PowerPC single-bit copy between CR bits, recognised by assemblers as the simplified mnemonic crmove BT, BA. This is the standard way to relocate a CR bit (e.g., promote cr1.EQ to cr0.EQ so a default-cr0 branch can consume it).
• Bit-level operands. Three independent 5-bit CR-bit indices; mixing CR fields is the whole point of this family.
• Use case. Branch on "A OR B" of two prior compare results — saves an extra branch by collapsing two conditions.
• No Rc / OE. Pure CR-bit dataflow.
• Not synchronising. Reorderable.
• xenia status. Most-used CR-logical instruction in real code (almost always as crmove). Decoded by the generic XL-form CR-logical handler; canary emits a host OR.

Related Instructions

• crand, crandc — AND family.
• crorc — OR with complement.
• crnor, crnand — negated forms.
• crxor, creqv — XOR / XNOR.
• mcrf — copy a 4-bit CR field wholesale.
• bcx, bclrx, bcctrx — typical consumers.

Simplified Mnemonics

Simplified	Expansion	Effect
crmove BT, BA	cror BT, BA, BA	CR[BT] ← CR[BA] (single-bit copy)

IBM Reference

• AIX 7.3 — cror (Condition Register OR)
• AIX 7.3 — Condition register simplified mnemonics