xenia-rs/migration/project-root/ppc-manual/control/mcrfs.md

# `mcrfs` — Move to Condition Register from FPSCR

> **Category:** [Control / CR / SPR](../categories/control.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0xfc000080`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `mcrfs` | `mcrfs` | — | Move to Condition Register from FPSCR |

## Syntax

```asm
mcrfs [CRFD], [CRFS]
```

## Encoding

### `mcrfs` — form `X`

- **Opcode word:** `0xfc000080`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `64`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `CRFS` | mcrfs: read | CR source field. |
| `FPSCR` | mcrfs: read; mcrfs: write | Floating-Point Status and Control Register. |
| `CRFD` | mcrfs: write | CR destination field (`crf`, 0–7). |

## Register Effects

### `mcrfs`

- **Reads (always):** `CRFS`, `FPSCR`
- **Reads (conditional):** _none_
- **Writes (always):** `CRFD`, `FPSCR`
- **Writes (conditional):** _none_

## Status-Register Effects

- `mcrfs`: **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`mcrfs`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="mcrfs"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:371`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L371)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:51`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L51)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:904`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L904)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4716-4745`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4716-L4745)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::mcrfs => {
            let crfd = instr.crfd();
            let crfs = instr.crfs();
            let shift = 28 - (crfs as u32 * 4);
            let nibble = ((ctx.fpscr >> shift) & 0xF) as u8;
            ctx.cr[crfd] = crate::context::CrField::from_u8(nibble);
            // Clearable exception bits: 0 (FX), 3 (OX), 4 (UX), 5 (ZX),
            // 6 (XX), 7 (VXSNAN), 8 (VXISI), 9 (VXIDI), 10 (VXZDZ),
            // 11 (VXIMZ), 12 (VXVC), 21 (VXSOFT), 22 (VXSQRT), 23 (VXCVI).
            // (Bit positions are PowerISA MSB-0; here 'FPSCR bit n' means
            // the bit at (31-n) in our little-endian u32.)
            const CLEARABLE_MASK: u32 =
                (1 << 31) | (1 << (31 - 3))  | (1 << (31 - 4))  |
                (1 << (31 - 5)) | (1 << (31 - 6))  | (1 << (31 - 7))  |
                (1 << (31 - 8)) | (1 << (31 - 9))  | (1 << (31 - 10)) |
                (1 << (31 - 11)) | (1 << (31 - 12)) |
                (1 << (31 - 21)) | (1 << (31 - 22)) | (1 << (31 - 23));
            let nibble_mask = 0xFu32 << shift;
            ctx.fpscr &= !(nibble_mask & CLEARABLE_MASK);
            // PPCBUG-068: recompute the VX summary bit. If any VX* exception
            // bit remains set, VX must remain set; if all are cleared, VX
            // must clear. (FEX recomputation omitted — xenia doesn't model
            // enabled-exception dispatch.)
            if ctx.fpscr & fpscr::VX_ALL != 0 {
                ctx.fpscr |= fpscr::VX;
            } else {
                ctx.fpscr &= !fpscr::VX;
            }
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Operation.** Copies one 4-bit FPSCR field into the chosen CR field, then **clears the source FPSCR exception-status bits** (sticky-bit reset). The non-exception status bits (FPRF, etc.) are *not* cleared.
- **Bits cleared in FPSCR.** The architectural rule is: any bit in the source FPSCR field that is one of {FX, OX, UX, ZX, XX, VXSNAN, VXISI, VXIDI, VXZDZ, VXIMZ, VXVC, VXSOFT, VXSQRT, VXCVI} is reset to 0 after the copy. FEX and VX (summary bits) are subsequently re-derived. Many other FPSCR bits (rounding mode, FPRF, FR/FI) are not affected — even if they fall in `CRFS`.
- **CR field destination.** `CRFD` is a 3-bit field index (0..7); the four bits land in their natural positions (LT, GT, EQ, SO) of the chosen CR field. After `mcrfs`, `crf` can be tested with the usual conditional branches.
- **Use case.** Inspect a particular FPSCR exception group, then act on it with a `bc` — e.g. test FPSCR[24..27] (the FI / FR / VXSNAN / VXISI cluster) and branch.
- **Privilege.** Non-privileged on the Xenon — application-visible.
- **xenia status.** Decoded (decoder slot 727), but the interpreter does **not** ship a body in the snapshot on this page — `mcrfs` is rare in title code. xenia's FPSCR model is incomplete (most exception bits are stubbed), so even when implemented, the cleared bits typically have no observable effect.
- **No `Rc`.** X-form, but the `Rc` bit position is unused (reserved 0).

## Related Instructions

- [`mffsx`](mffsx.md) — read entire FPSCR into an FPR.
- [`mtfsfx`](mtfsfx.md), [`mtfsb0x`](mtfsb0x.md), [`mtfsb1x`](mtfsb1x.md), [`mtfsfix`](mtfsfix.md) — write FPSCR bits/fields.
- [`mcrf`](mcrf.md) — copy a CR field to another CR field.
- [`mcrxr`](mcrxr.md) — analogous copy from XER (also clears).

`mcrfs` has no simplified mnemonics.

## IBM Reference

- [AIX 7.3 — `mcrfs` (Move to Condition Register from FPSCR)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-mcrfs-move-condition-register-from-fpscr-instruction)
- PowerISA v2.07B, Book I §4.6 — FPSCR layout (sticky exception bits and which clear semantics apply).