xenia-rs/migration/project-root/ppc-manual/control/mcrxr.md

mcrxr — Move to Condition Register from XER

Category: Control / CR / SPR · Form: X · Opcode: 0x7c000400

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mcrxr	mcrxr	—	Move to Condition Register from XER

Syntax

mcrxr [CRFD]

Encoding

mcrxr — form X

• Opcode word: 0x7c000400
• Primary opcode (bits 0–5): 31
• Extended opcode: 512
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
CR	mcrxr: read	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
CRFD	mcrxr: write	CR destination field (crf, 0–7).

Register Effects

mcrxr

• Reads (always): CR
• Reads (conditional): none
• Writes (always): CRFD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mcrxr

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="mcrxr"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_control.cc:433
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:51
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:814
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4694-4706

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::mcrxr => {
            let crfd = instr.crfd();
            ctx.cr[crfd] = crate::context::CrField {
                lt: ctx.xer_so != 0,
                gt: ctx.xer_ov != 0,
                eq: ctx.xer_ca != 0,
                so: false,
            };
            ctx.xer_so = 0;
            ctx.xer_ov = 0;
            ctx.xer_ca = 0;
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Operation. Copies XER's top 4 status bits into a CR field, then atomically clears those XER bits. Layout in the destination CR field after the move:

  CR bit	Source XER bit	Meaning
  LT	XER[SO]	summary overflow (sticky)
  GT	XER[OV]	overflow (last OE=1 op)
  EQ	XER[CA]	carry
  SO	0 (cleared)	—

• Sticky-bit reset. XER[SO], XER[OV], and XER[CA] are all zeroed after the copy. This is the only architecturally clean way to sample-then-clear XER's overflow/carry state — mfxer reads but does not clear.

• Use case. Saturating-arithmetic loops sample XER[OV] periodically; mcrxr cr0; bso cr0, overflow is the canonical "did overflow happen since last check?" idiom.

• CR field destination. CRFD is a 3-bit index (0..7). All other CR fields are preserved.

• No reads of GPRs. mcrxr reads only XER, writes only the chosen CR field and XER.

• xenia exact match. xenia-rs implements the full sample-and-clear semantics: writes lt = SO, gt = OV, eq = CA, so = false, then zeroes xer_so, xer_ov, xer_ca. Matches PowerISA exactly.

• Deprecated in newer PowerISA. PowerISA v2.06+ marked mcrxr deprecated in favour of mcrxrx and explicit mfxer/mtxer patterns, but the Xenon predates that; titles still emit it freely.

Related Instructions

• mfcr, mtcrf — bulk CR <-> GPR moves.
• mcrf — CR-field copy.
• mcrfs — analogous copy from FPSCR (also clears certain bits).
• mfspr (with SPR=1, i.e. mfxer) — non-clearing read of XER into a GPR.
• mtspr (with SPR=1, i.e. mtxer) — explicit XER write.

mcrxr has no simplified mnemonics.

IBM Reference

• AIX 7.3 — mcrxr (Move to Condition Register from XER)