xenia-rs/migration/project-root/ppc-manual/control/mtfsb0x.md

mtfsb0x — Move to FPSCR Bit 0

Category: Control / CR / SPR · Form: X · Opcode: 0xfc00008c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mtfsb0	mtfsb0x	—	Move to FPSCR Bit 0
mtfsb0.	mtfsb0x	Rc=1	Move to FPSCR Bit 0

Syntax

mtfsb0[Rc] [FPSCRD]

Encoding

mtfsb0x — form X

• Opcode word: 0xfc00008c
• Primary opcode (bits 0–5): 63
• Extended opcode: 70
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FPSCRD	mtfsb0x: write	FPSCR destination field.
CR	mtfsb0x: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

mtfsb0x

• Reads (always): none
• Reads (conditional): none
• Writes (always): FPSCRD
• Writes (conditional): CR

Status-Register Effects

• mtfsb0x: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mtfsb0x

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="mtfsb0x"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:406
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:55
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:905
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3055-3061

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::mtfsb0x => {
            // Clear FPSCR bit crbd
            let bit = instr.crbd();
            ctx.fpscr &= !(1 << (31 - bit));
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Operation. Clears (sets to 0) a single named bit of the 32-bit FPSCR. The bit is selected by FPSCRD (a 5-bit absolute index 0..31, big-endian: 0 = MSB = FX).
• The mnemonic name "Bit 0" is misleading. "0" refers to the value being written, not to bit position 0. Pair with mtfsb1x which writes a 1.
• Restricted bits. Per PowerISA, mtfsb0 cannot clear bits 1 (FEX) or 2 (VX) — those are summary bits, derived from other FPSCR bits. xenia-rs does not enforce this restriction; it will happily flip any bit. In practice no Xbox 360 title relies on the restriction's enforcement.
• Rc=1. mtfsb0. (Rc=1) updates CR1 with the high four FPSCR bits (FX, FEX, VX, OX) after the clear. This is the FPU's record-form analogue.
• Common use. Reset a sticky exception bit ahead of a sequence of FP ops you want to monitor (e.g. mtfsb0 5 to clear ZX before a divide series, then read it back).
• xenia simplification. xenia-rs maintains FPSCR as a u32 and does the bit clear correctly, but most downstream FP instructions in xenia do not update FPSCR exception bits — so monitoring them after mtfsb0 will see the bits stay at their seed value. Acceptable for titles that use FPSCR only to manage rounding / non-exception state.
• Not synchronising. Reorderable.

Related Instructions

• mtfsb1x — set a single FPSCR bit to 1.
• mtfsfx — write fields of FPSCR from an FPR.
• mtfsfix — write a 4-bit immediate into one FPSCR field.
• mffsx — read FPSCR.
• mcrfs — copy FPSCR field → CR field (and clear sticky bits).

mtfsb0 is itself the simplified form (Rc=0); mtfsb0. is the recording variant.

IBM Reference

• AIX 7.3 — mtfsb0 (Move to FPSCR Bit 0)
• PowerISA v2.07B, Book I §4.6 — FPSCR bit definitions and the FX/FEX/VX restriction.