xenia-rs/migration/project-root/ppc-manual/control/mtfsb1x.md

mtfsb1x — Move to FPSCR Bit 1

Category: Control / CR / SPR · Form: X · Opcode: 0xfc00004c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mtfsb1	mtfsb1x	—	Move to FPSCR Bit 1
mtfsb1.	mtfsb1x	Rc=1	Move to FPSCR Bit 1

Syntax

mtfsb1[Rc] [FPSCRD]

Encoding

mtfsb1x — form X

• Opcode word: 0xfc00004c
• Primary opcode (bits 0–5): 63
• Extended opcode: 38
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FPSCRD	mtfsb1x: write	FPSCR destination field.
CR	mtfsb1x: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

mtfsb1x

• Reads (always): none
• Reads (conditional): none
• Writes (always): FPSCRD
• Writes (conditional): CR

Status-Register Effects

• mtfsb1x: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mtfsb1x

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="mtfsb1x"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_fpu.cc:411
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:55
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:902
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3062-3068

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::mtfsb1x => {
            // Set FPSCR bit crbd
            let bit = instr.crbd();
            ctx.fpscr |= 1 << (31 - bit);
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Operation. Sets (writes 1 to) a single named bit of FPSCR. FPSCRD is a 5-bit absolute index (0..31), big-endian (0 = MSB = FX).
• Mnemonic name. "1" denotes the value written, not bit position. Pair with mtfsb0x for clears.
• Restricted bits. PowerISA forbids mtfsb1 from setting FEX (bit 1) or VX (bit 2) directly — both are summary bits derived from other state. mtfsb1 can set FX (bit 0), which is itself a sticky summary; this is occasionally used to force a Program interrupt for testing. xenia-rs does not enforce the restriction; setting summary bits will stick until cleared explicitly.
• Rc=1. mtfsb1. (Rc=1) updates CR1 with the high four FPSCR bits (FX, FEX, VX, OX) after the set.
• Common use. Force-set a sticky exception bit to test exception-handling code paths. Also seen in floating-point library setup that wants a known FPSCR seed.
• xenia simplification. Same caveat as mtfsb0: xenia maintains FPSCR but most FP paths don't read it, so the set has limited downstream effect. The bit will read back correctly via mffsx.
• Not synchronising. Reorderable.

Related Instructions

• mtfsb0x — clear a single FPSCR bit.
• mtfsfx — write 4-bit FPSCR fields from an FPR.
• mtfsfix — write 4-bit immediate into a single FPSCR field.
• mffsx — read FPSCR.
• mcrfs — FPSCR field → CR field (clears sticky bits).

mtfsb1 is the simplified form (Rc=0); mtfsb1. is the recording variant.

IBM Reference

• AIX 7.3 — mtfsb1 (Move to FPSCR Bit 1)
• PowerISA v2.07B, Book I §4.6 — FPSCR bit definitions and FX/FEX/VX restriction.