e6d43a23ac
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
138 lines
11 KiB
Markdown
138 lines
11 KiB
Markdown
# Form `VX` — VX — Vector (3-operand Altivec)
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## Bit Layout
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT/VD` | destination vector register |
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| 11–15 | `VRA/VA` | source A vector register |
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| 16–20 | `VRB/VB` | source B vector register |
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| 21–31 | `XO` | extended opcode (11 bits) |
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## Instructions Using This Form
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<!-- GENERATED: BEGIN -->
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| Mnemonic | Opcode | Group | Description |
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| --- | --- | --- | --- |
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| [`vaddubm`](../vmx/vaddubm.md) | `0x10000000` | vmx | Vector Add Unsigned Byte Modulo |
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| [`vmaxub`](../vmx/vmaxub.md) | `0x10000002` | vmx | Vector Maximum Unsigned Byte |
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| [`vrlb`](../vmx/vrlb.md) | `0x10000004` | vmx | Vector Rotate Left Integer Byte |
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| [`vmuloub`](../vmx/vmuloub.md) | `0x10000008` | vmx | Vector Multiply Odd Unsigned Byte |
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| [`vaddfp`](../vmx/vaddfp.md) | `0x1000000a` | vmx | Vector Add Floating Point |
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| [`vmrghb`](../vmx/vmrghb.md) | `0x1000000c` | vmx | Vector Merge High Byte |
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| [`vpkuhum`](../vmx/vpkuhum.md) | `0x1000000e` | vmx | Vector Pack Unsigned Half Word Unsigned Modulo |
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| [`vadduhm`](../vmx/vadduhm.md) | `0x10000040` | vmx | Vector Add Unsigned Half Word Modulo |
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| [`vmaxuh`](../vmx/vmaxuh.md) | `0x10000042` | vmx | Vector Maximum Unsigned Half Word |
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| [`vrlh`](../vmx/vrlh.md) | `0x10000044` | vmx | Vector Rotate Left Integer Half Word |
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| [`vmulouh`](../vmx/vmulouh.md) | `0x10000048` | vmx | Vector Multiply Odd Unsigned Half Word |
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| [`vsubfp`](../vmx/vsubfp.md) | `0x1000004a` | vmx | Vector Subtract Floating Point |
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| [`vmrghh`](../vmx/vmrghh.md) | `0x1000004c` | vmx | Vector Merge High Half Word |
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| [`vpkuwum`](../vmx/vpkuwum.md) | `0x1000004e` | vmx | Vector Pack Unsigned Word Unsigned Modulo |
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| [`vadduwm`](../vmx/vadduwm.md) | `0x10000080` | vmx | Vector Add Unsigned Word Modulo |
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| [`vmaxuw`](../vmx/vmaxuw.md) | `0x10000082` | vmx | Vector Maximum Unsigned Word |
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| [`vrlw`](../vmx/vrlw.md) | `0x10000084` | vmx | Vector Rotate Left Integer Word |
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| [`vmrghw`](../vmx/vmrghw.md) | `0x1000008c` | vmx | Vector Merge High Word |
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| [`vpkuhus`](../vmx/vpkuhus.md) | `0x1000008e` | vmx | Vector Pack Unsigned Half Word Unsigned Saturate |
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| [`vpkuwus`](../vmx/vpkuwus.md) | `0x100000ce` | vmx | Vector Pack Unsigned Word Unsigned Saturate |
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| [`vmaxsb`](../vmx/vmaxsb.md) | `0x10000102` | vmx | Vector Maximum Signed Byte |
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| [`vslb`](../vmx/vslb.md) | `0x10000104` | vmx | Vector Shift Left Integer Byte |
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| [`vmulosb`](../vmx/vmulosb.md) | `0x10000108` | vmx | Vector Multiply Odd Signed Byte |
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| [`vrefp`](../vmx/vrefp.md) | `0x1000010a` | vmx | Vector Reciprocal Estimate Floating Point |
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| [`vmrglb`](../vmx/vmrglb.md) | `0x1000010c` | vmx | Vector Merge Low Byte |
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| [`vpkshus`](../vmx/vpkshus.md) | `0x1000010e` | vmx | Vector Pack Signed Half Word Unsigned Saturate |
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| [`vmaxsh`](../vmx/vmaxsh.md) | `0x10000142` | vmx | Vector Maximum Signed Half Word |
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| [`vslh`](../vmx/vslh.md) | `0x10000144` | vmx | Vector Shift Left Integer Half Word |
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| [`vmulosh`](../vmx/vmulosh.md) | `0x10000148` | vmx | Vector Multiply Odd Signed Half Word |
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| [`vrsqrtefp`](../vmx/vrsqrtefp.md) | `0x1000014a` | vmx | Vector Reciprocal Square Root Estimate Floating Point |
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| [`vmrglh`](../vmx/vmrglh.md) | `0x1000014c` | vmx | Vector Merge Low Half Word |
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| [`vpkswus`](../vmx/vpkswus.md) | `0x1000014e` | vmx | Vector Pack Signed Word Unsigned Saturate |
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| [`vaddcuw`](../vmx/vaddcuw.md) | `0x10000180` | vmx | Vector Add Carryout Unsigned Word |
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| [`vmaxsw`](../vmx/vmaxsw.md) | `0x10000182` | vmx | Vector Maximum Signed Word |
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| [`vslw`](../vmx/vslw.md) | `0x10000184` | vmx | Vector Shift Left Integer Word |
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| [`vexptefp`](../vmx/vexptefp.md) | `0x1000018a` | vmx | Vector 2 Raised to the Exponent Estimate Floating Point |
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| [`vmrglw`](../vmx/vmrglw.md) | `0x1000018c` | vmx | Vector Merge Low Word |
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| [`vpkshss`](../vmx/vpkshss.md) | `0x1000018e` | vmx | Vector Pack Signed Half Word Signed Saturate |
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| [`vsl`](../vmx/vsl.md) | `0x100001c4` | vmx | Vector Shift Left |
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| [`vlogefp`](../vmx/vlogefp.md) | `0x100001ca` | vmx | Vector Log2 Estimate Floating Point |
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| [`vpkswss`](../vmx/vpkswss.md) | `0x100001ce` | vmx | Vector Pack Signed Word Signed Saturate |
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| [`vaddubs`](../vmx/vaddubs.md) | `0x10000200` | vmx | Vector Add Unsigned Byte Saturate |
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| [`vminub`](../vmx/vminub.md) | `0x10000202` | vmx | Vector Minimum Unsigned Byte |
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| [`vsrb`](../vmx/vsrb.md) | `0x10000204` | vmx | Vector Shift Right Byte |
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| [`vmuleub`](../vmx/vmuleub.md) | `0x10000208` | vmx | Vector Multiply Even Unsigned Byte |
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| [`vrfin`](../vmx/vrfin.md) | `0x1000020a` | vmx | Vector Round to Floating-Point Integer Nearest |
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| [`vspltb`](../vmx/vspltb.md) | `0x1000020c` | vmx | Vector Splat Byte |
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| [`vupkhsb`](../vmx/vupkhsb.md) | `0x1000020e` | vmx | Vector Unpack High Signed Byte |
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| [`vadduhs`](../vmx/vadduhs.md) | `0x10000240` | vmx | Vector Add Unsigned Half Word Saturate |
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| [`vminuh`](../vmx/vminuh.md) | `0x10000242` | vmx | Vector Minimum Unsigned Half Word |
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| [`vsrh`](../vmx/vsrh.md) | `0x10000244` | vmx | Vector Shift Right Half Word |
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| [`vmuleuh`](../vmx/vmuleuh.md) | `0x10000248` | vmx | Vector Multiply Even Unsigned Half Word |
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| [`vrfiz`](../vmx/vrfiz.md) | `0x1000024a` | vmx | Vector Round to Floating-Point Integer toward Zero |
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| [`vsplth`](../vmx/vsplth.md) | `0x1000024c` | vmx | Vector Splat Half Word |
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| [`vupkhsh`](../vmx/vupkhsh.md) | `0x1000024e` | vmx | Vector Unpack High Signed Half Word |
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| [`vadduws`](../vmx/vadduws.md) | `0x10000280` | vmx | Vector Add Unsigned Word Saturate |
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| [`vminuw`](../vmx/vminuw.md) | `0x10000282` | vmx | Vector Minimum Unsigned Word |
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| [`vsrw`](../vmx/vsrw.md) | `0x10000284` | vmx | Vector Shift Right Word |
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| [`vrfip`](../vmx/vrfip.md) | `0x1000028a` | vmx | Vector Round to Floating-Point Integer toward +Infinity |
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| [`vspltw`](../vmx/vspltw.md) | `0x1000028c` | vmx | Vector Splat Word |
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| [`vupklsb`](../vmx/vupklsb.md) | `0x1000028e` | vmx | Vector Unpack Low Signed Byte |
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| [`vsr`](../vmx/vsr.md) | `0x100002c4` | vmx | Vector Shift Right |
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| [`vrfim`](../vmx/vrfim.md) | `0x100002ca` | vmx | Vector Round to Floating-Point Integer toward -Infinity |
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| [`vupklsh`](../vmx/vupklsh.md) | `0x100002ce` | vmx | Vector Unpack Low Signed Half Word |
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| [`vaddsbs`](../vmx/vaddsbs.md) | `0x10000300` | vmx | Vector Add Signed Byte Saturate |
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| [`vminsb`](../vmx/vminsb.md) | `0x10000302` | vmx | Vector Minimum Signed Byte |
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| [`vsrab`](../vmx/vsrab.md) | `0x10000304` | vmx | Vector Shift Right Algebraic Byte |
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| [`vmulesb`](../vmx/vmulesb.md) | `0x10000308` | vmx | Vector Multiply Even Signed Byte |
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| [`vcfux`](../vmx/vcfux.md) | `0x1000030a` | vmx | Vector Convert from Unsigned Fixed-Point Word |
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| [`vspltisb`](../vmx/vspltisb.md) | `0x1000030c` | vmx | Vector Splat Immediate Signed Byte |
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| [`vpkpx`](../vmx/vpkpx.md) | `0x1000030e` | vmx | Vector Pack Pixel |
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| [`vaddshs`](../vmx/vaddshs.md) | `0x10000340` | vmx | Vector Add Signed Half Word Saturate |
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| [`vminsh`](../vmx/vminsh.md) | `0x10000342` | vmx | Vector Minimum Signed Half Word |
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| [`vsrah`](../vmx/vsrah.md) | `0x10000344` | vmx | Vector Shift Right Algebraic Half Word |
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| [`vmulesh`](../vmx/vmulesh.md) | `0x10000348` | vmx | Vector Multiply Even Signed Half Word |
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| [`vcfsx`](../vmx/vcfsx.md) | `0x1000034a` | vmx | Vector Convert from Signed Fixed-Point Word |
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| [`vspltish`](../vmx/vspltish.md) | `0x1000034c` | vmx | Vector Splat Immediate Signed Half Word |
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| [`vupkhpx`](../vmx/vupkhpx.md) | `0x1000034e` | vmx | Vector Unpack High Pixel |
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| [`vaddsws`](../vmx/vaddsws.md) | `0x10000380` | vmx | Vector Add Signed Word Saturate |
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| [`vminsw`](../vmx/vminsw.md) | `0x10000382` | vmx | Vector Minimum Signed Word |
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| [`vsraw`](../vmx/vsraw.md) | `0x10000384` | vmx | Vector Shift Right Algebraic Word |
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| [`vctuxs`](../vmx/vctuxs.md) | `0x1000038a` | vmx | Vector Convert to Unsigned Fixed-Point Word Saturate |
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| [`vspltisw`](../vmx/vspltisw.md) | `0x1000038c` | vmx | Vector Splat Immediate Signed Word |
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| [`vctsxs`](../vmx/vctsxs.md) | `0x100003ca` | vmx | Vector Convert to Signed Fixed-Point Word Saturate |
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| [`vupklpx`](../vmx/vupklpx.md) | `0x100003ce` | vmx | Vector Unpack Low Pixel |
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| [`vsububm`](../vmx/vsububm.md) | `0x10000400` | vmx | Vector Subtract Unsigned Byte Modulo |
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| [`vavgub`](../vmx/vavgub.md) | `0x10000402` | vmx | Vector Average Unsigned Byte |
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| [`vand`](../vmx/vand.md) | `0x10000404` | vmx | Vector Logical AND |
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| [`vmaxfp`](../vmx/vmaxfp.md) | `0x1000040a` | vmx | Vector Maximum Floating Point |
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| [`vslo`](../vmx/vslo.md) | `0x1000040c` | vmx | Vector Shift Left by Octet |
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| [`vsubuhm`](../vmx/vsubuhm.md) | `0x10000440` | vmx | Vector Subtract Unsigned Half Word Modulo |
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| [`vavguh`](../vmx/vavguh.md) | `0x10000442` | vmx | Vector Average Unsigned Half Word |
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| [`vandc`](../vmx/vandc.md) | `0x10000444` | vmx | Vector Logical AND with Complement |
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| [`vminfp`](../vmx/vminfp.md) | `0x1000044a` | vmx | Vector Minimum Floating Point |
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| [`vsro`](../vmx/vsro.md) | `0x1000044c` | vmx | Vector Shift Right Octet |
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| [`vsubuwm`](../vmx/vsubuwm.md) | `0x10000480` | vmx | Vector Subtract Unsigned Word Modulo |
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| [`vavguw`](../vmx/vavguw.md) | `0x10000482` | vmx | Vector Average Unsigned Word |
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| [`vor`](../vmx/vor.md) | `0x10000484` | vmx | Vector Logical OR |
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| [`vxor`](../vmx/vxor.md) | `0x100004c4` | vmx | Vector Logical XOR |
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| [`vavgsb`](../vmx/vavgsb.md) | `0x10000502` | vmx | Vector Average Signed Byte |
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| [`vnor`](../vmx/vnor.md) | `0x10000504` | vmx | Vector Logical NOR |
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| [`vavgsh`](../vmx/vavgsh.md) | `0x10000542` | vmx | Vector Average Signed Half Word |
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| [`vsubcuw`](../vmx/vsubcuw.md) | `0x10000580` | vmx | Vector Subtract Carryout Unsigned Word |
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| [`vavgsw`](../vmx/vavgsw.md) | `0x10000582` | vmx | Vector Average Signed Word |
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| [`vsububs`](../vmx/vsububs.md) | `0x10000600` | vmx | Vector Subtract Unsigned Byte Saturate |
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| [`mfvscr`](../control/mfvscr.md) | `0x10000604` | control | Move from VSCR |
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| [`vsum4ubs`](../vmx/vsum4ubs.md) | `0x10000608` | vmx | Vector Sum Across Partial (1/4) Unsigned Byte Saturate |
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| [`vsubuhs`](../vmx/vsubuhs.md) | `0x10000640` | vmx | Vector Subtract Unsigned Half Word Saturate |
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| [`mtvscr`](../control/mtvscr.md) | `0x10000644` | control | Move to VSCR |
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| [`vsum4shs`](../vmx/vsum4shs.md) | `0x10000648` | vmx | Vector Sum Across Partial (1/4) Signed Half Word Saturate |
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| [`vsubuws`](../vmx/vsubuws.md) | `0x10000680` | vmx | Vector Subtract Unsigned Word Saturate |
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| [`vsum2sws`](../vmx/vsum2sws.md) | `0x10000688` | vmx | Vector Sum Across Partial (1/2) Signed Word Saturate |
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| [`vsubsbs`](../vmx/vsubsbs.md) | `0x10000700` | vmx | Vector Subtract Signed Byte Saturate |
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| [`vsum4sbs`](../vmx/vsum4sbs.md) | `0x10000708` | vmx | Vector Sum Across Partial (1/4) Signed Byte Saturate |
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| [`vsubshs`](../vmx/vsubshs.md) | `0x10000740` | vmx | Vector Subtract Signed Half Word Saturate |
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| [`vsubsws`](../vmx/vsubsws.md) | `0x10000780` | vmx | Vector Subtract Signed Word Saturate |
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| [`vsumsws`](../vmx/vsumsws.md) | `0x10000788` | vmx | Vector Sum Across Signed Word Saturate |
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<!-- GENERATED: END -->
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