xenia-rs/migration/project-root/ppc-manual/vmx128/vmaddcfp128.md

vmaddcfp128 — Vector128 Multiply Add Floating Point

Category: VMX128 · Form: VX128 · Opcode: 0x14000110

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmaddcfp128	vmaddcfp128	—	Vector128 Multiply Add Floating Point

Syntax

vmaddcfp128 [VD], [VA], [VD], [VB]

Encoding

vmaddcfp128 — form VX128

• Opcode word: 0x14000110
• Primary opcode (bits 0–5): 5
• Extended opcode: 272
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vmaddcfp128: read	Source A vector register.
VD	vmaddcfp128: read; vmaddcfp128: write	Destination vector register.
VB	vmaddcfp128: read	Source B vector register.

Register Effects

vmaddcfp128

• Reads (always): VA, VD, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmaddcfp128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="vmaddcfp128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:812
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:100
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:614
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:4492-4509

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::vmaddcfp128 => {
            // ISA: (VD) <- (VA × VD) + VB. Canary InstrEmit_vmaddcfp128 (cc:819): MulAdd(VA, VD, VB).
            // Previous code computed di.mul_add(bi, ai) = VD×VB+VA — both operands wrong
            // (PPCBUG-425). Fix: ai.mul_add(di, bi) = VA×VD+VB.
            let a = ctx.vr[instr.va128()].as_f32x4();
            let b = ctx.vr[instr.vb128()].as_f32x4();
            let d = ctx.vr[instr.vd128()].as_f32x4();
            let mut r = [0f32; 4];
            for i in 0..4 {
                let ai = vmx::flush_denorm(a[i]);
                let bi = vmx::flush_denorm(b[i]);
                let di = vmx::flush_denorm(d[i]);
                // PPCBUG-437: flush subnormal output too.
                r[i] = vmx::flush_denorm(ai.mul_add(di, bi));
            }
            ctx.vr[instr.vd128()] = xenia_types::Vec128::from_f32x4_array(r);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Xbox-specific fused multiply-add variant. Each lane computes VD[i] = VD[i] * VB[i] + VA[i] — note that VD is both source and destination (xenia reads VD first, then writes). This is not the standard vmaddfp operand order: the "addend" position is VA, the other factor is VB, and VD carries the on-going accumulator. The mnemonic's trailing c denotes "accumulator-in-VD" rather than a separate VC operand.
• Fused, single-rounding. Xenia uses f32::mul_add, which maps to a host FMA instruction when available. Bit-for-bit result depends on host support; xenia-canary's LLVM path emits the equivalent IR node.
• IEEE-754 binary32 lanes; VSCR[NJ] honoured.
• No VSCR[SAT], no FPSCR update.
• NaN propagation per IEEE-754.
• VMX128 register-fusion (7-bit IDs on VA, VB, VD).
• No IBM AIX entry — Xenon-only.
• No Rc, no XER.

Related Instructions

• vmaddfp, vmaddfp128 — standard fused (VA × VC) + VB.
• vmulfp128 — plain lane-wise float multiply.
• vnmsubfp — negative-multiply-subtract.
• vmsum3fp128, vmsum4fp128 — dot-product reductions.

IBM Reference

• No IBM AIX entry — this is an Xbox 360 VMX128 extension. Its semantics differ from the base Altivec vmaddfp in the operand order (accumulator in VD, not VC).
• Xbox 360 XDK, Altivec-128 (VMX128) extensions.
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic for the base FMA semantics.